Peter D. MacWilliams

Method and apparatus for implementing multiple memory buses on a memory module

Method for implementing multiple memory buses on a memory module

Second level cache controller unit and system

Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system

Method and apparartus for sharing a signal line between agents

Method and apparatus for performing deferred transactions

Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus

Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path

Highly pipelined bus architecture

Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit