Peter Deane
National Semiconductor
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Publication
Featured researches published by Peter Deane.
Microelectronics Reliability | 1998
Albert Wang; Chen H. Tsay; Amit Lele; Peter Deane
A full-scale simulation-aided ESD design methodology was used to design a group of NMOS ESD protection units. Silicon results match the simulation data quite well. Both simulation and measurement data show good ESD performance uniformity across NMOS poly finger length and finger number in ladder structures in a large range. Optimal layout pattern for ladder structures was obtained with the aid of simulation.
Archive | 2009
Peter Smeys; Peter Johnson; Peter Deane
Archive | 1999
Albert Wang; Chen H. Tsay; Peter Deane
Archive | 2003
Peter Deane; Euan P. Livingston
Archive | 2004
Luu Thanh Nguyen; Ken Pham; Peter Deane; William Paul Mazotti; Bruce Carlton Roberts; Jia Liu
Archive | 2000
Luu Nguyen; Cade Murray; Peter Deane; Chen-Hui Tsay
Archive | 2006
Peter Deane
Archive | 2001
Albert Wang; Chen H. Tsay; Peter Deane
Archive | 2007
Peter Deane
Archive | 2003
Hsin-Ho Wu; Peter Deane