Peter Duzy

High-level synthesis from VHDL with exact timing constraints

The authors present a solution to the interface timing problem in high-level synthesis by requiring that the algorithmic specification must completely determine the interface timing on the basis of cycles. They explain the timing problem and discuss the solution, which is closely related to a specific subset of the very high-speed IC description language (VHDL). This approach has been integrated into the high-level synthesis system CALLAS. An overview is given of the synthesis techniques of CALLAS. Controller reduction, which is the key transformation for satisfying the timing constraints, is discussed. The algorithms are formally described. The timing concept is compared to other approaches. Experimental results are provided.<<ETX>>

ASIC design using the high-level synthesis system CALLAS: a case study

The Siemens high-level synthesis system CALLAS was used to synthesize an ASIC for moving-object detection consisting of 3400 equivalent gates. The digital signal processing (DSP) problem was formulated on algorithmic level in the hardware description language DSDL as a three-page algorithm. Only a few days were needed from specification to the chip layout. Design steps included were high-level behavior simulation, library mapping, and standard cell layout generation using a state-of-the-art physical design system. The authors give a brief overview of the CALLAS system, introduce the DSP example, and discuss the synthesis process and the simulations performed.<<ETX>>

The CALLAS synthesis system and its application to mechatronic ASIC design problems

The authors demonstrate the use of high-level synthesis for ASIC designs in the mechatronic application domain. The first chip synthesized and fabricated is part of a distance measurement system. Only six weeks were needed for the design of the 2700 equivalent gates ASIC. The hand-crafted standard cell design had taken four times as long for a result of comparable size and performance. Similar results have been obtained in a second ASIC project, which is part of a friction clutch controller.<<ETX>>