Peter H. Hochschild

The SP2 high-performance switch

The heart of an IBM SP2™ system is the HighPerformance Switch, which is a low-latency, highbandwidth switching network that binds together RISC System/6000® processors. The switch incorporates a unique combination of topology and architectural features to scale aggregate bandwidth, enhance reliability, and simplify cabling. It is a bidirectional multistage interconnect subsystem driven by a common oscillator, and delivers both data and service packets over the same links. Switching elements contain a dynamically allocated shared buffer for storing blocked packet flits. The switch is constructed primarily from switching elements (the Vulcan switch chip) and adapters (the SP2 communication adapter). The SP2 communication adapter uses a variety of techniques to improve bandwidth and offload communication tasks from the node processor. This paper examines the switch architecture and presents an overview of its support software.

The communication software and parallel environment of the IBM SP2

This paper describes the software available on the IBM SP2™ for parallel program development and execution. It presents the rationale for the design of the Message-Passing Library used on the SP2, outlines its current implementation, and gives information on performance. In addition, the paper describes the programming environment and the program development tools available for developing and executing parallel codes.

The SP1 high-performance switch

The IBM scalable POWERparallel systems 9076 SP1 connects RISC System/6000 processors via a communication network called the high-performance switch. This switch-based upon the Vulcan parallel processor incorporates a number of unusual features to enhance reliability, diagnose faults, and simplify cabling. This paper examines the SP1 switch architecture and implementation and overviews the switch support software. The switch is a bidirectional MIN, and provides at least 4 usable redundant paths for most pairs of communicating nodes.<<ETX>>

Architecture and implementation of Vulcan

IBMs recently announced Scalable POWERparallel family of systems is based upon the Vulcan architecture, and the currently available 9076 SP1 parallel system utilizes fundamental Vulcan technology. The experimental Vulcan parallel processor is designed to scale to many thousands of microprocessor-based nodes. To support a machine of this size, the nodes and network incorporate a number of unusual features to scale aggregate bandwidth, enhance reliability, diagnose faults, and simplify cabling. The multistage Vulcan network is a unified data and service network driven by a single oscillator. An attempt is made to detect all network errors via cyclic redundancy checking (CRC) and component shadowing. Switching elements contain a dynamically allocated shared buffer for storing blocked packet flits from any input port. This paper describes the key elements of Vulcans hardware architecture and implementation details of the Vulcan prototype.<<ETX>>

An Efficient Implementation of MPI

MPI-F, a prototype high-performance implementation of MPI on the IBM SPI is described and MPI-F communication performance is presented.

MPI on IBM SP1/SP2: current status and future directions

A complete prototype implementation of MPI on the IBM Scalable Power PARALLEL 1 and 2 (SP1, SP2) is discussed. This implementation achieves essentially the same performance as the native EUI library, although MPI is much larger. The paper describes the implementation of EUI on SP1/SP2, and the modifications required to to implement MPI, initial performance measurements, and directions for future work.<<ETX>>

Breaking the connection: RDMA deconstructed

The architecture, design and performance of RDMA (remote direct memory access) over the IBM HPS (high performance switch and adapter) are described. Unlike conventional implementations such as InfiniBand, our RDMA transport model is layered on top of an unreliable datagram interface, while leaving the task of enforcing reliability to the ULP (upper layer protocol). We demonstrate that our model allows a single MPI task to deliver bidirectional bandwidth of close to 3.0 GB/s across a single link and 24.0 GB/s when striped across 8 links. In addition, we show that this transport protocol has superior attributes in terms of a) being able to handle RDMA packets coming out of order; b) being able to use multiple routes between a source-destination pair and c) reducing the size of adapter caches.

Interactive parallel visualization framework for distributed data

A framework for parallel visualization at Pacific Northwest National Laboratory (PNNL) is being developed that utilizes the IBM Scaleable Graphics Engine (SGE) and IBM SP parallel computers. Parallel visualization resources are discussed, including display technologies, data handling, rendering, and interactivity. Several of these resources have been developed, while others are under development. These framework resources will be utilized by programmers in custom parallel visualization applications.

Scalable visualization using a network-attached video framebuffer

Abstract We present a scalable, commodity-based, parallel rendering system for interactive visualization of large polygonal and volumetric data models. Our system utilizes commodity PCs that have multiple CPUs and high-capacity I/O buses, a fast AGP bus, and a commodity interconnect. Rendering occurs in parallel using the Chromium framework with the resulting images displayed over the network on a remote display. A key component of our system is the Scalable Graphics Engine, a network-attached video framebuffer capable of gathering pixels from up to 16 sources and driving multiple displays. Our experimental results show that recent developments in commodity computers favor parallel architectures designed to use framebuffer readback and pixel transfer over commodity networks versus specialized hardware for acquiring and aggregating pixel data.