Peter J. Meier

FAST LOCK CLOCK-DATA RECOVERY FOR PHASE STEPS

Modal PAM2/4 Pipelined Programmable Receiver Having Feed Forward Equalizer (FFE) And Decision Feedback Equalizer (DFE) Optimized For Forward Error Correction (FEC) Bit Error Rate (BER) Performance

System and Method For Adaptive N-Phase Clock Generation For An N-Phase Receiver

Internal Loop-Back Architecture For Parallel Serializer/Deserializer (SERDES)

Modal PAM2/PAM4 Divide By N (Div-N) Automatic Correlation Engine (ACE) For A Receiver

System and method for high speed data parallelization for an N-phase receiver

Integrated Circuit Design Method for Efficiently Generating Mask Data

Low power parallelization to multiple output bus widths

Modale PAM2/PAM4 geteilt durch N (Div-N) automatische Korrelationsmaschine (ACE) für einen Empfänger Modal PAM2 / PAM4 divided by N (Div-N) automatic correlation engine (ACE) for a receiver

Quick lock clock data recovery for Phase Steps