Peter L. Bird

Improving code density using compression techniques

Proposes a method for compressing programs in embedded processors where the instruction memory size dominates the cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM and i386 instruction sets and achieve an average size reduction of 39%, 34% and 26%, respectively, for SPEC CINT95 programs.

The effectiveness of decoupling

This paper examines the effectiveness of decoupling as an optimization technique for high-performance computer architectures. Decoupled access execute architectures are described, and the concept of control decoupling is introduced and justified. A description of a highly-decoupled architecture is given, and a metric for the effectiveness of decoupling on particular programs, the Loss of Decoupling frequency is introduced. Finally, a number of real benchmark programs are examined and the applicability of decoupling them is analyzed.

Compiling and Optimizing for Decoupled Architectures

Decoupled architectures provide a key to the problem of sustained supercomputer performance through their ability to hide large memory latencies. When a program executes in a decoupled mode the perceived memory latency at the processor is zero; effectively the entire physical memory has an access time equivalent to the processors register file, and latency is completely hidden. However, the asynchronous functional units within a decoupled architecture must occasionally synchronize, incurring a high penalty. The goal of compiling and optimizing for decoupled architectures is to partition the program between the asynchronous functional units in such a way that latencies are hidden but synchronization events are executed infrequently. This paper describes a model for decoupled compilation, and explains the effectiveness of compilation for decoupled systems. A number of new compiler optimizations are introduced and evaluated quantitatively using the Perfect Club scientific benchmarks. We show that with a suitable repertiore of optimizations, it is possible to hide large latencies most of the time for most of the programs in the Perfect Club.

A Comparison of Two Memory Models for High Performance Computers

High performance scientific computers require high bandwidth memory systems. The size of data sets for large scientific codes implies the need for a memory system which contains independent, interleaved banks. We compare the performance of two different control structures for an interleaved memory: bank buffering and address stream lookahead. We show that a centralized lookahead memory controller provides equivalent memory performance to a bank buffering system while simplifying implementation.

An implementation of a code generator specification language for table driven code generators

This paper discusses an implementation of Glanvilles code generator generator for producing a code generator for a production Pascal compiler on an Amdahl 470. We successfully replaced the hand written code generator of an existing compiler with one which was produced automatically from a formal specification. This paper first outlines Glanvilles original scheme, then describes extensions which were necessary for generating code for a production compiler.

Using Lookahead to reduce memory bank contention for decoupled operand references

No abstract available

A semantics-directed partitioning of a processor architecture

No abstract available

Linear time detection of inherent parallelism in sequential programs

Abstract The topological sort can be used for the rapid detection of parallelism in sequential programs. Using this algorithm, one can detect both intrablock and interblock parallelism. The algorithm requires only information normally collected by an optimizing compiler.