Peter Maria Franciscus Rombouts

PRINCE: a low-latency block cipher for pervasive computing applications

This paper presents a block cipher that is optimized with respect to latency when implemented in hardware. Such ciphers are desirable for many future pervasive applications with real-time security needs. Our cipher, named PRINCE, allows encryption of data within one clock cycle with a very competitive chip area compared to known solutions. The fully unrolled fashion in which such algorithms need to be implemented calls for innovative design choices. The number of rounds must be moderate and rounds must have short delays in hardware. At the same time, the traditional need that a cipher has to be iterative with very similar round functions disappears, an observation that increases the design space for the algorithm. An important further requirement is that realizing decryption and encryption results in minimum additional costs. PRINCE is designed in such a way that the overhead for decryption on top of encryption is negligible. More precisely for our cipher it holds that decryption for one key corresponds to encryption with a related key. This property we refer to as α-reflection is of independent interest and we prove its soundness against generic attacks.

Low-latency encryption: is Lightweight = light + wait?

The processing time required by a cryptographic primitive implemented in hardware is an important metric for its performance but it has not received much attention in recent publications on lightweight cryptography. Nevertheless, there are important applications for cost effective low-latency encryption. As the first step in the field, this paper explores the low-latency behavior of hardware implementations of a set of block ciphers. The latency of the implementations is investigated as well as the trade-offs with other metrics such as circuit area, time-area product, power, and energy consumption. The obtained results are related back to the properties of the underlying cipher algorithm and, as it turns out, the number of rounds, their complexity, and the similarity of encryption and decryption procedures have a strong impact on the results. We provide a qualitative description and conclude with a set of recommendations for aspiring low-latency block cipher designers.

Low-Latency ECDSA Signature Verification—A Road Toward Safer Traffic

Car-to-car and car-to-infrastructure messages exchanged in intelligent transportation systems can reach reception rates over 1000 messages per second. As these messages contain elliptic curve digital signature algorithm (ECDSA) signatures, this puts a very heavy load onto the verification hardware. In fact, the load is so high that, currently, it can only be achieved by implementations running on high-end CPUs and field-programmable gate arrays. These implementations are far from cost-effective or energy efficient. In this paper, we present an application-specified integrated circuit implementation of a dedicated ECDSA verification engine that can reach verification rates of up to 27 000 verifications per second, which is by far the fastest implementation on a single core reported in the literature.