Peter Paul Frans Reusens

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-held terminals

The modulator IC has been designed to integrate all analog baseband processing components of the European Groupe Special Mobile (GSM) digital cellular radio terminals onto a single component. The IC is located at the interface of the analog 900-MHz radio-frequency part and the baseband digital signal processing part of the mobile terminal. The modulator part time-multiplexes the receive and transmit operations and combines low-noise receive circuitry with a digital modulator. The device uses digital waveform generation and a balanced quadrature representation for both modulation and demodulation of the Gaussian minimum-shift-keying (GMSK) signal. To enhance testability of the high-density printed-circuit boards, advanced test features have also been implemented in the modulator IC. In the transmit direction, the modulator IC converts digitally encoded speech or data at an instantaneous rate of 270 kb/s to the I (in-phase) and Q (quadrature) analog signals which are used to modulate a 900-MHz carrier.<<ETX>>

Single chip DMT-modem transceiver for ADSL

The complete digital processing of the Discrete Multitone modulation technique has been integrated into a single device, processed in 0.5 /spl mu/m standard CMOS. The optimal power and area result (realized by algorithmic optimisations) and the extended programmability make this component the basis to build cost effective ADSL systems.

A power efficient channel coder/decoder chip for GSM terminals

A compact power and computing delay efficient channel codec chip for the pan-European digital cellular radio (Group Special Mobile, or GSM) system is presented. This key component for the hand-portable mobile station is realized through a dedicated architecture and application-tailored memories. Full scan design and self-test facilities result in time and coverage efficient testing. This chip was developed in 1.2- mu m CMOS technology. The power, size, and processing time compare favorably to those for any standard processor-based implementation.<<ETX>>

A practical ADSL technology following a decade of effort

This article offers a behind the scenes glimpse of a successful ADSL transceiver development, completed over the last decade while the ADSL standard evolved. It discusses the pitfalls experienced by designers and describes how a pragmatic and unconventional design solution was found.

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2- mu m CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW. >

A rate adaption coprocessor for terminal adapters with U-interface modems

A rate adapter is described which provides a compact cost- and power-efficient means of connecting any data terminal by means of the integrated services digital network (ISDN). In contrast to previous solutions, this chip supports both single and multichannel applications. In single-channel applications, the rate adapter chip and an 8-bit microcontroller with RAM and ROM implement a complete system. In multichannel applications, up to 256 rate adapters can connect to one PCM (pulse-code modulation) highway without any additional hardware. Statistical subchannel multiplexing compliant with CCITT recommendations G.704 and I.460 is easily realized owing to the integrated programmable bus adapter and a flexible bandwidth assignment. The rate adapter was designed in a 2- mu m double-metal CMOS technology. The 50 k-transistor device dissipates 80 mW in worst-case conditions. The rate adapter chip is a key building block in a 144-kb/s U-modem. Connecting rate adapters in parallel to a single-chip U-interface circuit allows the time-division multiplexing of up to 16 data terminals onto one full-duplex two-wire 155-kb/s link. As a result, this system provides a low-cost access to the ISDN for existing terminal equipment.<<ETX>>

A clock/data extraction device for use in ATM electro-optical networks

A device designed for clock extraction in an ATM optical network for a fiber in the loop system operating at 155/622 Mb/s is presented. The device applies a new clock phase alignment technique to recover the clock/data signal from up to 16 remote nodes.<<ETX>>

A Monolithic Channel Coder/Decoder Chip For GSW Terminals

A compact, power and computing delay efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the handportable Mobile Station is accomplished through a dedicated architecture and application taylored memories. Full scan design and selftest facilities result in time and coverage efficient testing.

A viable multi-standard rate adapter chip for ISDN communications

A multistandard rate adapter coprocessor chip designed using 2 mu m CMOS technology for use in integrated services digital network (ISDN) terminal adapters and U-interface modems is presented. It provides a compact, low-power protocol converter to connect asynchronous (up to 19200-bit/s) and synchronous (up to 64-kbit/s) data terminal equipment with any digital 64-kbit/s network. The connection to the ISDN is established through an S-interface or a U-interface circuit. This rate adapter is the cornerstone of a 144-kbit/s U-interface modem and a major breakthrough for the next-generation multistandard terminal adapter.<<ETX>>

A rate adaption gateway to the ISDN

A multistandard rate adapter coprocessor chip, designed for use in integrated services digital network (ISDN) terminal adapters and U-interface modems, is presented. It provides a compact low-power protocol convertor to connect asynchronous (up to 19200 b/s) and synchronous (up to 64 kbit/s) data terminal equipment with any digital 64-kbit/s network. The chip was developed in a 2- mu m CMOS technology using a hierarchical design methodology. The chip provides a compact cost- and power-efficient solution for universal-terminal adapter design. The rate adapter is the cornerstone of a 144-kbit/s U-interface modem and a major breakthrough for the next-generation multistandard terminal adapter.<<ETX>>