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Archive | 1995

Formal Semantics for VHDL

Carlos Delgado Kloos; Peter T. Breuer

From the Publisher: It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several commercially- and academically-based tools. Having different tools and users generating and reading the same language requires that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity is very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in Formal Methods and can be used as a text for an advanced course on the subject.


Z User Workshop | 1994

Towards Correct Executable Semantics for Z

Peter T. Breuer; Jonathan P. Bowen

There are many ad hoc tools aimed at the animation of executable subsets of the formal specification language Z. This paper presents an approach to rigorously establishing the correctness of such Z animation tools, drawing on ideas from the field of abstract interpretation. Enough of the standard Z syntax is treated to cover most uses of Z schemas and expressions, after schema calculus constructs have been expanded and embedded schema references replaced.


ACM Transactions on Programming Languages and Systems | 1994

Decompilation: the enumeration of types and grammars

Peter T. Breuer; Jonathan P. Bowen

While a compiler produces low-level object code from high-level source code, a decompiler produces high-level code from low-level code and has applications in the testing and validation of safety-critical software. The decompilation of an object code provides an independent demonstration of correctness that is hard to better for industrial purposes (an alternative is to prove the compiler correct). But, although compiler compilers are in common use in the software industry, a decompiler compiler is much more unusual. It turns out that a data type specification for a programming-language grammar can be remolded into a functional program that enumerates all of the abstract syntax trees of the grammar. This observation is the springboard for a general method for compiling decompilers from the specifications of (nonoptimizing) compilers. This paper deals with methods and theory, together with an application of the technique. The correctness of a decompiler generated from a simple occam-like compiler specification is demonstrated. The basic problem of enumerating the syntax trees of grammars, and then stopping, is shown to have no recursive solution, but methods of abstract interpretation can be used to guarantee the adequacy and completeness of our technique in practical instances, including the decompiler for the language presented here.


Software - Practice and Experience | 1995

A PREttier compiler-compiler: generating higher-order parsers in C

Peter T. Breuer; Jonathan P. Bowen

Top‐down (LL) context‐sensitive parsers with integrated synthesis and use of attributes are easy to express in functional programming languages, but the elegant functional programming model can also serve as an exact prototype for a more efficient implementation of the technology in ANSI C. The result is a compiler‐compiler that takes unlimited lookahead and backtracking, the extended BNF notation, and parameterized grammars with (higher‐order) meta‐parameters to the world of C programming. This article reports on the utility in question three years after public release. Precc generates standard ANSI C and is ‘plug compatible’ with lex‐ generated lexical analyzers prepared for the UNIX yacc compiler‐compiler. In contrast to yacc, however, the generated code is modular, which allows parts of scripts to be compiled separately and linked together incrementally. The constructed code is relatively efficient, as is demonstrated by the example Occam parser treated in depth here, but the main advantages we claim are ease of use, separation of specification and implementation concerns, and maintainability.


international conference on reliable software technologies | 2004

Static Deadlock Detection in the Linux Kernel

Peter T. Breuer; Marisol García Valls

This article describes a C code static analyser that detects misuse of spinlocks in the Linux kernel. Spinlock misuse is difficult to detect by testing, relatively common, and leads to runtime deadlocks in the Linux operating system kernel on multiprocessor architectures.


formal methods | 1995

A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL

Peter T. Breuer; Luis Sánchez Fernández; Carlos Delgado Kloos

A denotational semantics and a Hoare programming logic for a subset of the standard hardware description languageVHDL are set out here. Both define the behaviour of synchronously clockedVHDL simulators in declarative and compositional style. The logic is proved complete with respect to the denotational semantics and a natural implementation of the logic inPROLOG as a validation condition generator forVHDL is also described.The subset of the language referred to above essentially consists of elaboratedVHDL excluding only deltadelayed signal assignments and zero waits. However, for brevity, only one of the two forms ofVHDL signal assignment is treated here. Moreover, for simplicity, signal resolution functions and local state are assumed to have been encoded away via expressions and signals.


Software Engineering Journal | 1993

A compendium of formal techniques for software maintenance

Jonathan P. Bowen; Peter T. Breuer; Kevin Lano

Software maintenance is an important area in practical software engineering that has been largely overlooked by many theoretical computer scientists. This paper gives an overview of formal techniques developed recently to aid the software maintenance process, and in particular reverse engineering and re-engineering. In the future, it is suggested that specifications, rather than programs, should be maintained. The described work provides a mathematical basis for a large collaborative project, which has also been investigating many other aspects of software maintenance.


Information & Software Technology | 1993

Formal specifications in software maintenance: from code to Z++ and back again

Jonathan P. Bowen; Peter T. Breuer; Kevin Lano

Abstract The paper presents a number of techniques that have been developed as components of the software maintenance process as part of the ESPRIT REDO project. These techniques are all based on formal methods, and the work described has provided the mathematical underpinning to a large collaborative project that has been investigating various aspects of software maintenance. The focus of the project has been on reverse engineering, and methods for this part of the maintenance process are reported on here, along with techniques for subsequent re-engineering. A proposal for specification-oriented software maintenance is presented, in which specifications in an object-oriented extension of the formal notation Z are maintained in step with the corresponding programs.


european design and test conference | 1994

Clean formal semantics for VHDL

Peter T. Breuer; Luis Sánchez Fernández; Carlos Delgado Kloos

A simple formal semantics for the standard hardware description language VHDL is set out in functional style. The presentation comprises an executable specification for a synchronously clocked VHDL simulator.<<ETX>>


ACM Transactions on Programming Languages and Systems | 1997

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

Peter T. Breuer; Carlos Kloos Delgado; Andrés Marín; Natividad Martínez Madrid; Luis Sánchez Fernández

A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is “correct by construction”. the calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general. That logic and a semantics for a core subset of VHDL are described. The programming logic and the associated refinement calculus are shown to be complete. This means that if there is a code that can be shown to implement a given specification, then it will be derivable from the specification via the calculus.

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Jonathan P. Bowen

London South Bank University

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Esther Palomar

Birmingham City University

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Luis Sánchez

Technical University of Madrid

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A. Royo

Technical University of Madrid

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M.L. Lopez

Technical University of Madrid

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Simon Pickin

Complutense University of Madrid

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