Phan C. Vinh

Continuity aspects of embedded reconfigurable computing

Abstract.In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.

Formalization of data flow computing and a coinductive approach to verifying flowware synthesis

Reconfigurable computing refers to the notions of configware and flowware. Configware means structural programming, or programming in space to execute computation in space. Flowware means dataflow programming that schedules the data flow for output from or input to the configware architecture. In this paper, data flows of a synthesized computation are formalized. This means that data flow is specified as a behavioral stream function in stream calculus, which is used to underpin the semantics for Register Transfer Level (RTL) synthesis. A stream representation allows the use of coinductive principles in stream calculus. In particular, using the coinductive proof principle, we show that behavioral stream functions in the three-stage synthesis process (scheduling, register allocation and binding, allocation and binding of functional units) are always bisimilar regardless of changes in a scheduling, allocation or binding procedure. Our formalization makes pipelining possible, in which all functional units as well as registers of hardware resources are reused during different control steps (C-steps). Moreover, a coinductive approach to verifying flowware synthesis, which is independent of the heuristic during register allocating and binding step, is proposed as a practical technique.

Semantics of RTL and validation of synthesized RTL designs using formal verification in reconfigurable computing systems

The functional validation of a state-of-the-art reconfigurable computing system design is usually a laborious, ad hoc and open-ended task. It can be accomplished through two basic approaches: simulation and formal verification. In validation using a formal verification approach, it attempts to establish that the register transfer level (RTL) design synthesized from the algorithmic behavioral specification is mathematically correct. Therefore, finding the verification methods to provide accurate and fast validation easily would be very useful. In this paper, we develop a semantics based on a partial order based model (POM) for RTL and, through this semantics, propose a formal verification method to prove the correctness of the RTL synthesis result. This method can be used to achieve the following. On one hand, it can accurately verify an RTL description with respect to a behavioral specification of the system; on the other hand, it can decide whether two processes, which are supposed to implement the same function, have the same interactive behaviors, so that one can be replaced by the other.

An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs

Efficient management of the logic resource available is one of the biggest problems faced by the embedded systems based on FPGA, in which their functionality can be partially modified at run-time without stopping the operation of the whole system. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. Dynamical reconfiguration can be necessary to relocate a running physical configuration, and to rearrange the logic resources into the variety of physical portions. Our proposed algorithm is formally developed to enable implementing an on-line management of FPGA logic resources, supporting the rearrangement of running functions, releasing enough contiguous space for configuration of new incoming functions, and performing the defragmentation in a way completely transparent to the applications currently running. Therefore, on-line scheduling of tasks in the spatial and temporal domains becomes possible, enabling the implementation of virtual hardware concept.

RETRACTED: On the Visual Representation of Configuration in Reconfigurable Computing

This article has been retracted at the request of the Editor in Chief. Reason: it was found to have used material from other sources without proper attribution. The editors have been advised by Dr. Nathaniel Miller (University of Northern Colorado) that a major portion of the paper - On the Visual Representation of Configuration in Reconfigurable Computing - which appears in the proceedings, was copied from his 2001 Cornell University PhD thesis - A Diagrammatic Formal System for Euclidean Geometry. The editors have checked the paper against Dr. Millers thesis, and find his claims to be valid. . A logical configuration is provable from another one by applying these rules.

A Provable Algorithm for Reconfiguration in Embedded Reconfigurable Computing

Dynamically reconfigurable computing within embedded computer-based systems can be partially modified at runtime without stopping the operation of the whole system. In this paper, a provable algorithm for runtime evolution of a logical configuration is formally represented by the appropriate graph transformation. In other words, programming is considered as a visual transformation of the logical configuration by the formulated rules. Their soundness is proved. A logical configuration in evolution is provable from another by applying these rules. Subsequently, an algorithmic approach to programming is formally developed and analyzed