Philip Godoy

A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS

We present a 2.4-GHz asymmetric multilevel outphasing (AMO) power amplifier (PA) with class-E branch amplifiers and discrete supply modulators integrated in a 65-nm CMOS process. AMO PAs achieve improved modulation bandwidth and efficiency over envelope tracking (ET) PAs by replacing the continuous supply modulator with a discrete supply modulator implemented with a fast digital switching network. Outphasing modulation is used to provide the required fine output envelope control. The AMO PA delivers 27.7-dBm peak output power with 45% system efficiency at 2.4 GHz. For a 20-MHz WLAN OFDM signal with 7.5-dB PAPR, the AMO PA achieves a drain efficiency of 31.9% and a system efficiency of 27.6% with an EVM of 2.7% rms.

Asymmetric multilevel outphasing architecture for multi-standard transmitters

We describe a new outphasing transmitter architecture in which the supply voltage for each PA can switch among multiple levels. It is based on a new asymmetric multilevel outphasing (AMO) modulation technique which increases overall efficiency over a much wider output power range than the standard LINC system while maintaining high linearity. For demonstration, the overall transmitter is simulated in a 65nm CMOS process with HSUPA and WLAN signals. The simulation results show an efficiency improvement from 17.7% to 40.7% for HSUPA at 25.3dBm output power and from 11.3% to 35.5% for WLAN 802.11g at 22.8dBm while still meeting system linearity requirements.

20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput

The steep growth of digital-content consumption and increasing reliance on wireless networks has resulted in emerging standards such as IEEE 802.11ac. By employing spatial diversity, Multi-user MIMO and high-density modulation (up to 256-QAM), 802.11ac MIMO radios can provide significantly increased throughput, link robustness, and range while maintaining backward-compatibilities with existing 802.11a/n WLAN [1]. However, wide signal bandwidth and high-density modulation lead to significant challenges in all aspects of RF transceiver design, compared to previous WLAN standards. This paper introduces a fully integrated 3-stream MIMO WLAN SoC that integrates all of the functions of an 802.11a/b/g/n/ac WLAN with a record over-the-air TCP/IP throughput of 1.1Gb/s. The 40nm CMOS SoC integrates dual-band (2.4GHz and 5GHz) RF transceivers, data converters, digital physical layer, media access controller, and a PCI Express Gen-2 interface. The RF transceiver employs an all-digital fractional-N PLL with a record Figure-of-Merit (FoM) of -244dB, a wideband low-impedance bias circuit that minimizes pre-PA driver memory effect for 80MHz signal bandwidth, a dual-band receiver with 3dB/4.3dB NF, and a 5th-order Chebyshev low-pass filter with constant-Gm bias and pre-distorted filter coefficients to support up to 80MHz signal bandwidth.

A highly efficient 1.95-GHz, 18-W asymmetric multilevel outphasing transmitter for wideband applications

A 1.95-GHz asymmetric multilevel outphasing (AMO) transmitter with class-E GaN power amplifiers (PAs) and discrete supply modulators is presented. AMO transmitters achieve improved efficiency over envelope tracking (ET) transmitters by replacing the continuous supply modulator with a discrete supply modulator implemented with a fast digital switching network. Outphasing modulation is used to provide the required fine output envelope control. A 4-level supply modulator is implemented that allows for fast and efficient discrete envelope modulation with up to 28-V supply voltages using low-voltage gate drivers and time-alignment logic. With two class-E GaN PAs that achieve 62.5% power-added efficiency (PAE) at 40- dBm peak output power, the AMO transmitter delivers 42.6- dBm peak output power at 1.95-GHz. For a 16-QAM signal at 36-dBm output power, the transmitter achieves 44.2/42.8/41.4% average system efficiency and 2.0/2.1/3.1% EVM for 10/20/40-MHz channel bandwidth, respectively.

9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation

The 2×2 wireless LAN (WLAN) + Bluetooth (BT) combo chip continues to be the most versatile product category in the wireless connectivity space. It finds usage in a wide range of applications, such as laptops, tablets, high-end smartphones, gaming consoles, set-top boxes, wireless routers and in-car/personal hot-spot devices. Digital-intensive SoCs have been relying on Moores law to keep the cost down. However, traditional RF and analog circuits are facing more difficulties to keep up with Moores law due to the physical constraint of inductors, capacitors, and resistors. To overcome these difficulties, we leveraged digital and mixed-signal techniques to architect the transceiver, with a WLAN Digital PA (DPA), a WLAN All-Digital PLL (ADPLL), a BT ADPLL with pulling cancellation, and a high-speed SAR-ADC with reduced analog filter order in the WLAN RX.

Asymmetric multilevel outphasing transmitter using class-E PAs with discrete pulse width modulation

We present a high-efficiency transmitter architecture based on asymmetric multilevel outphasing (AMO), but with a new method of generating discrete amplitude levels from the constituent amplifiers. AMO and multilevel LINC (ML-LINC) transmitters improve their efficiency over LINC by switching the supplies of the power amplifiers (PAs) among a discrete set of voltages. This allows them to minimize the occurrence of large outphasing angles. However, it is also possible to generate a discrete set of amplitudes by varying the duty cycle of the waveform that drives the PAs. The chief advantage of this discrete pulse width modulation (DPWM) is hardware simplicity, as it eliminates the need for a fast, low-loss switching network and a selection of power supply voltages. We demonstrate this concept with a 48-MHz, 20-W peak output power AMO transmitter using a four-level DPWM. At peak output power, the measured power-added efficiency is 77.7%. For a 16-QAM signal with a 6.5-dB peak-to-average power ratio, the AMO prototype improves the average efficiency from 17.1% to 36.5% compared to the standard LINC system.

Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers

We describe a general offset-canceling architecture for analog multiplication using chopper stabilization. Chopping is used to modulate the offset away from the output signal where it can be easily filtered out, providing continuous offset reduction which is insensitive to drift. Both square wave chopping and chopping with orthogonal spreading codes are tested and shown to reduce the offset down to the microvolt level. In addition, we apply the nested chopping technique to an analog multiplier which employs two levels of chopping to reduce the offset even further. We discuss the limits on the performance of the various chopping methods in detail, and present a detailed analysis of the residual offset due to charge injection spikes. An illustrative CMOS prototype in a 0.18 mum process is presented which achieves a worst-case offset of 1.5 muV. This is the lowest measured offset reported in the DC analog multiplier literature by a margin of two orders of magnitude. The prototype multiplier is also tested with AC inputs as a squarer, variable gain amplifier, and direct-conversion mixer, demonstrating that chopper stabilization is effective for both DC and AC multiplication. The AC measurements show that chopping removes not only offset, but also 1/f noise and second-order harmonic distortion.

A 12-bit resolution, 200-MSample/second phase modulator for a 2.5GHz carrier with discrete carrier pre-rotation in 65nm CMOS

A digital-to-RF phase modulator based on a single current-steering DAC is presented, including a carrier pre-rotation scheme that prevents phase inaccuracy due to carrier feedthrough. The phase modulator has been fabricated in a standard 65-nm CMOS process and draws 1.9 mW from a 1-V supply. The modulator achieves 12-bit resolution at a measured 200 MSamples/second, state-of-the-art performance in both resolution and sampling speed. It has sufficient speed to allow for oversampling to shape the output spectrum and therefore reduce filtering requirements, as demonstrated through a 32x oversampled 8-PSK signal at 6.25 MSymbols/second with under 6.1% EVM.

A dual core power combining digital power amplifier for 802.11b/g/n with +26.8dBm linear output power in 28nm CMOS

This paper presents a digital power amplifier with two cores that are power combined for a Psat of +32.5dBm. Assisted by an on-chip digital pre-distortion, a transmitted output power of +26.8dBm for 802.11g 54 Mbps 64-QAM is achieved. This is the highest reported linear output power for a digital power amplifier designed for 802.11b/g/n applications in bulk 28nm CMOS. A total area of 0.36mm2 is used for the power amplifier cores and combiner. Drawing off of a 3.3V supply, this power amplifier has a drain efficiency of 21.2% at the maximum linear output power.

13.7 A 0.23mm 2 digital power amplifier with hybrid time/amplitude control achieving 22.5dBm at 28% PAE for 802.11g

Integration of digital RF transmitters and digital power amplifiers (DPA) is becoming of great interest for systems-on-chip (SoCs) available in nanometer technologies [1]. Small and high-speed switching devices directly benefit switching power amplifiers in achieving peak power with high peak efficiency. However PA back-off efficiency remains a big challenge in high-data-rate systems with large peak-to-average ratio (PAR) such as in WLAN. Different solutions have been published to enhance power backoff efficiency but at a cost of higher complexity and larger area [2,3].