Philipp Häfliger

Neuromorphic silicon neuron circuits

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory–Processing– Learning–Actuating System for High-Speed Visual Object Recognition and Tracking

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asynchronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45 k neurons (spiking cells), up to 5 M synapses, performs 12 G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long term average signals are computed on the chip. We show the rules rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR systemIn this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long term average signals are computed on the chip. We show the rules rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system

A foveated AER imager chip [address event representation]

We have developed a foveated imager chip with high resolution photo-cells (referred to as static pixels) in the center that are surrounded by more space consuming adaptive change detection pixels (referred to as dynamic pixels). Inspired by the neurons of biological nervous systems, they emit short voltage pulses, the static pixels with a frequency proportional to light intensity, the dynamic pixels whenever they detect a relative change in irradiance. The pulses are transmitted off-chip by the address event representation (AER) protocol, i.e. via a digital bus as the identifying address of the sending pixel. For the motion pixels, this read-out strategy has the advantage of low latency in the order of 100 ns after a change is encountered. (Whereas a scanning read-out strategy would on average suffer a delay of half of the frame scanning period.) Mounted on a pan-tilt system, the peripheral motion detectors could, for instance, be used to steer the imager such that the image of a moving object falls onto the central pixel array where it can then be examined in detail at a higher resolution. Or, if the imager is mounted statically, they can detect an intruder and cause the central pixels to be turned on for more detailed observation

A Sub-

A new current-mode bandgap reference circuit (BGR) which is capable of generating sub-1-V output voltage is presented. It has not only the lowest theoretical minimum current consumption among published current-mode BGRs, but also additional advantages of an inherent curvature-compensation function and not requiring NPN BJTs. The curvature-compensation is achieved by utilizing the exponential behavior of sub-threshold CMOS transistors to compensate the BJT base-emitter voltage high-order temperature dependence. By taking advantages of the continuing development of CMOS technology, sub- μW power consumption is achieved with a reasonable core area. Related design considerations and challenges are discussed and analyzed. The proposed BGR is realized in a TSMC 90 nm process. Measurement results shows a temperature coefficient without trimming as low as 10.1 ppm/°C over a temperature range of 70 °C because of the proposed curvature-compensation technique. The average value is 32.6 ppm/°C which could be improved by trimming resistor ratios. The average power consumption at room temperature is 576 nW, with a core area of only 0.028 mm2.

\mu{\rm W}

The paper presents a high speed serial address-event representation (AER) link with a capacity of 41.66Mevents/sec. The link has been implemented using a low voltage differential signaling (LVDS) interface on a commercial FPGA. Many of the latest reconfigurable devices (FPGAs, CPLDs, etc.) offer highly optimized modules for this kind of communication. However, many AER processing systems require an ASIC implementation. The paper proposed to implement AER components with a serial AER interface as multi-chip PCBs with one or several ASICs communicating in parallel with an FPGA that handles the external high speed serial link. The authors judge the design effort to be much smaller than in a comparable monolithic ASIC implementation.

Bandgap Reference Circuit With an Inherent Curvature-Compensation Property

Background: The growing pandemic of diabetes mellitus places a stringent social and economic burden on the society. A tight glycemic control circumvents the detrimental effects, but the prerogative is the development of new more effective tools capable of longterm tracking of blood glucose (BG) in vivo. Such discontinuous sensor technologies will benefit from an unprecedented marked potential as well as reducing the current life expectancy gap of eight years as part of a therapeutic regime. Method: A sensor technology based on osmotic pressure incorporates a reversible competitive affinity assay performing glucose-specific recognition. An absolute change in particles generates a pressure that is proportional to the glucose concentration. An integrated pressure transducer and components developed from the silicon micro- and nanofabrication industry translate this pressure into BG data. Results: An in vitro model based on a 3.6 × 8.7 mm large pill-shaped implant is equipped with a nanoporous membrane holding 4–6 nm large pores. The affinity assay offers a dynamic range of 36–720 mg/dl with a resolution of ±16 mg/dl. An integrated 1 × 1 mm2 large control chip samples the sensor signals for data processing and transmission back to the reader at a total power consumption of 76 μW. Conclusions: Current studies have demonstrated the design, layout, and performance of a prototype osmotic sensor in vitro using an affinity assay solution for up to four weeks. The small physical size conforms to an injectable device, forming the basis of a conceptual monitor that offers a tight glycemic control of BG.

High-Speed Serial AER on FPGA

A time-domain winner-take-all circuit based on simple self-resetting integrate-and-fire neurons is presented in this paper. Integrate-and-fire (I&F) neurons can translate the intensity of a current input into a time domain signal: strong input current will lead to an early spike output and weak input to a late output. By making the self-reset line global for all neurons, only the first spiking neuron, which is the neuron with the strongest input, will ever spike, and thus, win over the others. This WTA circuits was conceived as part of an imager chip to process current input from a motion detection array, thus detecting the row and column of maximum change of illumination. The fact that this WTA processes analog input and produces spike output is most convenient for the address event interface (AER) and that conveys the WTA output off-chip. We verified the WTA functionality with experiments of an AMS 0.6 /spl mu/m CMOS implementation. Some suggestions on how to achieve additional functions by simple extensions of the circuit are discussed.

Toward an Injectable Continuous Osmotic Glucose Sensor

In this paper we present a VLSI implementation of learning synapse that that uses a spike based learning rule to adjust its weight. The weight is stored on a recently presented weak multi-level static memory cell (MLSM) by Hafliger and Riis (see ibid., May 2003). This memory cell stores a voltage on a capacitance and that voltage is weakly driven to the closest of several stable levels. We verified the suitability of this memory for this task in a VLSI chip implementation. An array of integrate and fire neurons with four of these learning synapse each was implemented on a 0.6 /spl mu/m AMS CMOS chip. The learning capability of these neurons was tested in simple spike and rate based pattern recognition tasks in a two neuron network. Cross-inhibition between them lead to improved decorrelation of the output spikes, inducing a tendency in the neurons to specialize on different patterns.

A time domain winner-take-all network of integrate-and-fire neurons

We have developed an ultra low power integrated circuit control module that will be incorporated into a micro machined pill-sized medical implant that continuously monitors blood-sugar levels for patients with Diabetes mellitus. The circuit converts a piezoresistive sensor signal to an inter-pulse interval suited for digital transmission through a wire-less inductive link. Instead of a full analog-to-digital conversion, this analog-to-analog conversion is much simpler and more power conservative. The circuit is entirely asynchronous, requiring no energy consuming clock and operates on sub-threshold currents. A first prototype, produced with the STM 90 nm CMOS process, consumes 1.7muW. A compact on-chip resistive element is employed in a feedback loop to cancel 1/f-noise and offsets in both the sensor and the initial amplification stage. The resistive element is implemented using the quantum effect of gate-leakage, achieving an equivalent resistance of several GOmega with minimal consumption of layout space. The effectiveness of this noise reduction has been asserted in a 62 hour recording with fixed input. The measured noise spectrum appears completely white down to the minimal frequency of the recording, i.e. 4.5muHz. The standard deviation of single pulse intervals (dynamic range from 4.3ms to 15.4 ms) restricts the reconstruction of the sensor value to an accuracy equivalent to 4.41 bits. Averaging over the samples during 1 second increases this accuracy to 7.84 bits. Longer averaging will further improve that figure at the cost of longer periods of active power consumption of the implant, which will be woken up only once every 5 minutes.