Philippe Baudesson

Layout techniques for reduction of common mode current in static converters

The radiation is, for the most part, generated by common-mode currents. This paper shows that action on layout can reduce common-mode currents effectively. Cost-effective, the common-mode current control enables the radiation level knowledge at the conception of a device. This is an important gain of time. Four boost structures are studied in order to validate first, experimentally and second by modelling, reduction common-mode current layouts, supposed effective. The simulated models are based on the partial equivalent element circuit (PEEC) method. We show also the impact of these layout techniques on radiated perturbations

Reduction of Common Mode Currents Generated by Three-Level Inverters with Consideration of Motor Overvoltages

In adjustable speed drive applications, the switching of the inverter semiconductors generates common mode currents as well as harmful overvoltages on the motor terminals when long cables are used. Consequently, bulky and expensive input and output filters must be used. This work aims at reducing these disturbances from their origin by using a three-level neutral-point-clamped (NPC) inverter controlled with a new pulse-width-modulation (PWM) strategy. Whereas previous common mode noise-reducing strategies usually generate higher overvoltages than conventional ones, the proposed PWM is able to manage both problems thanks to its internal degrees of freedom.

Implantation par porteuses d'une stratégie MLI réduisant les courants de mode commun générés par un onduleur NPC

This paper presents a new pulse-width-modulation strategy for the reduction of common-mode currents in adustable-speed-drive applications using a three-level neutral pointclamped inverter. It is implemented through a saw-tooth carrier-based modulator which makes it possible to control the degrees of freedom provided by the strategy.