Philippe Galy

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

ESD robustness of FDSOI gated diode for ESD network design: Thin or thick BOX?

The robustness against Electrostatic Discharge (ESD) events of gated diodes, fabricated in CMOS 45nm FDSOI technology, is compared for 10nm and 145nm Buried Oxide (BOX) thickness. It is shown that the performance of devices for co-design on thin BOX is improved thanks to a better thermal dissipation: A gain of 1.6 on the robustness was found.

In-Depth Electromagnetic Analysis of ESD Protection for Advanced CMOS Technology During Fast Transient and High-Current Surge

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections + silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more.

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. The paper presents a comparison between four ESD protections in CMOS 32 nm node. Dynamic and static triggering circuits are investigated and SCR and bi-SCR are compared. Each structure is characterized through TLP and protects up to 2 kV HBM stresses.

Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology

The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be compared. Also, the power pad clamps in 1 pitch IO are qualified through 100ns TLP. Silicon result show that ESD robustness reaches 4kV HBM, 200V MM and 500V CDM for a 64 BGA package. IO power pads are also immune to Latch Up and power sequence.

Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies

Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices

We present a full physical simulation picture of the electromagnetic phenomena combining electromagnetic (EM) fields and carrier transport in semiconductor devices (TCAD) in the transient regime. The simulation tool computes the EM fields in a self-consistent way and the resulting magnetic fields are incorporated in the computation of the current sources that get modified by the Lorentz force (LF).

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

SRAM bitcell optimizations have been demonstrated in 28nm High-k Metal Gate UTBB (Ultra-Thin Body and BOX) FD-SOI technology. The back-gate terminal biasing leads to forward or reverse bias of the transistors and has been used to improve the bitcell electrical metrics. The derived 6T bitcell variants show a gain of 67% (25%) in cell current at 0.6V (1V), 45% reduction in write time at 0.6V, along with a gain in either write margin or static noise margin. Two 4T load-less bitcell variants using back-gate bias have been fabricated and compared for performance, power and stability margins. The back-gate biasing concept has been extended to optimize 8T, 10T bitcells and their simulation results are also presented.

Beta-Matrix ESD network: Throughout end of placement rules?

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some constraint on IO and particularly on the frame and the placement in IO ring. In this context we develop and propose an ESD network with Beta-Matrix power device and its own trigger circuit which are integrated in each IO. We obtain a new local strategy which allows removing all IO placement constraint.

Impact of back plane on the carrier mobility in 28nm UTBB FDSOI devices, for ESD applications

We present measurements and parameter extraction performed on 28nm UTBB FDSOI MOSFETs with two different Back Plane configurations (p-type and n-type BP). The change in BP doping and work function affects directly the back-channel characteristics and indirectly, via interface coupling, the front-channel properties. We investigate the parameters relevant for the design of ESD protection devices: threshold voltage shift and electron mobility in long and short transistors.