Philippe Meunier-Beillard

On the Use of a SiGe Spike in the Emitter to Improve the

Aggressive vertical scaling of SiGe HBTs has yielded impressive values for the cut-off frequencies (fT), but these HBTs often suffer from too high current gains. This leads to low values for the open-base breakdown voltage (BVCEO). In this letter we demonstrate the use of a SiGe spike in the emitter as a practical method to increase the base current. Hence, the breakdown voltage is increased. At the same time, the device RF performance is not affected, which leads to a significant improvement in the fTxBVCEO product

f_{T}\hbox{xBV}_{\rm CEO}

Tensile strained Si on SiGe Strain Relaxed Buffers (SRB) is an interesting candidate to increase both electron and hole mobility which results in improved device performance. Most of this work was/is based on thick (several μm), step-graded SRBs with or without Chemical Mechanical Polishing (CMP) planarisation. This approach bears several disadvantages such as issues with STI formation in the thick SiGe structure, and considerable self-heating effects due to the lower thermal conductivity of the SiGe material. Further, pMOS improvement requires SRBs with high Ge contents (> 30 %), which complicates device fabrication even more. To overcome these issues, we developed a new and cost efficient type of thin SRB (∼200 nm). The concept is based on the introduction of a thin carbon-containing layer during growth of a constant composition SiGe layer. The process relies on standard Chemical Vapor Deposition epitaxial technology without need for CMP. It is designed to allow both non-selective growth on blanket wafers and selective growth in the active area of structured wafers with Shallow Trench Isolation (STI). The selective epitaxial process for strained Si on thin SRBs proposed here, allows relatively simple and cost-effective fabrication of strained Si layers on existing STI structures without any process modification. Further, it offers a very flexible fabrication scheme to independently improve nMOS and pMOS devices. The SRB quality is comparable to the best reported in literature so far, with 70 % and 53 % mobility enhancements for long channel nMOSFETs on 22 % Ge SRBs grown on blanket and STI patterned wafers, respectively.

Product of High-Speed SiGe HBTs

Junctions were formed in thin SiGe/strained Si substrates with a thickness of 250-350 nm to assess the effect of different buffer layer parameters (bandgap, dislocations, thickness) on the junction leakage density that can be expected in MOSFET devices. The implantations used are standard well, channel and Highly Doped Drain (HDD) implants. Both p + /n and n+/p junctions were evaluated. The total thickness of the buffer layers was varied to compare the effect of different structural layers on the diode leakage. This investigation shows that the effect of an increased defect density is dominant at room temperature for the strained Si samples, resulting in 4-5 orders of magnitude increase in leakage. However, there is a different gradation in leakage dependence for thick and thin buffer layers, especially at higher temperatures.