Philippe Perdu

Backside laser testing of ICs for SET sensitivity evaluation

A new experimental approach combining backside laser testing and analog mapping is presented. A new technique for integrated circuits (ICs) backside preparation by laser ablation is evaluated. The methodology is applied to the study of single-event transient (SET) sensitivity on a linear IC.

Delay variation mapping induced by dynamic laser stimulation

We present a novel technique based on dynamic laser stimulation (DLS) to characterize CMOS structures and to highlight time margin alterations by delay variation mapping. We used photoelectric laser stimulation (PLS) or thermal laser stimulation (TLS) to perturb CMOS transistor characteristics in order to affect propagation delays. The proposed methodology further extends the capabilities of DLS techniques such as soft defect localization (SDL) and laser assisted device alteration (LADA) to characterize defective ICs.

Dynamic Thermal Laser Stimulation Theory and Applications

Thermal laser stimulation (TLS) techniques have demonstrated their ability to detect and locate defects in integrated circuits (IC). Optical beam induced resistance change (OBIRCH) and all derivatives are based on the same physical principle: local laser heating of integrated circuits. The purpose of this paper is to synthesize the extensive work done in this area in order to highlight the essential physical principles. With this knowledge dynamic thermal laser stimulation (D-TLS) applications can then be tackled, optimizing parameters such as laser dwell time for sufficient heating. Finally, applications are presented on 180nm, 120nm and 90nm, comparing the sensitivity of dynamic thermal laser stimulation with respect to light emission

Magnetic microscopy for 3D devices: Defect localization with high resolution and long working distance on complex system in package.

Abstract As microelectronic technologies continue to develop according to the More than Moore’s law, so that full systems can be confined inside one assembly, failure analysis must take this into account. Magnetic microscopy has achieved successful failure analysis of standard ICs but now it faces new challenges related to the lack of resolution triggered by the long working distances necessary when working on complex 3D architectures. Our new approach can push the present scope of the technique further by using a simulation approach, and by measuring not only the z component of the magnetic field but also the x and the y by tilting the sample. We will show how we can map and localize defects with an increased resolution taking into account three-dimensional geometries.

Time Resolved Imaging: From logical states to events, a new and efficient pattern matching method for VLSI analysis

Time Resolved Imaging (TRI) allows real time imaging of transitions in CMOS gates even for very deep submicron technologies at low power supply voltage. Anyway, the measured timing information differs from waveform measurement where logical states are easily extracted. We first introduce logical event with a 1 value when we have transition from one logical state to its complement (0-1 or 1-0) or 0 value when there is no change between 2 vectors. Events can be extracted from TRI database and then used for a very accurate and efficient pattern matching method. In this paper, we demonstrate how we move from logical state to events and the extreme accuracy of pattern matching. Results are shown on 45 nm CMOS technology.

A review of sample backside preparation techniques for VLSI

Abstract A review of backside sample preparation techniques is presented. These techniques cover mechanical, chemical and other novel approaches such as laser ablation for ceramic and plastic package opening, silicon thinning and silicon polishing. To illustrate the milling process, we present two challenging backside sample preparation examples on a ceramic package and on a TSOP package.

Oxide charge measurements in EEPROM devices

Abstract A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical AFM based techniques (Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM)) are used to probe directly floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the data reveals to be the key point, more than the probing technique itself.

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

Abstract The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology.

Frequency mapping in dynamic light emission with wavelet transform

Abstract Dynamic photon emission microscopy is an efficient tool to analyse today’s integrated circuit. Nevertheless, the reduction of transistor’s dimensions leads to more complex acquisitions where many spots can be seen. A frequency characterization of the whole acquired area can help to have a better understanding of it. With that purpose in mind, a new methodology to draw frequency mapping of dynamic light emission acquisition is reported. It is fully automated and based on wavelet transform and autocorrelation function. Regarding the possible use in an industrial context, the suggested method can help to localize abnormal emission activity and it gives some perspectives on automatic databases comparison.

Light Emission to Time Resolved Emission For IC Debug and Failure Analysis

Light emission is routinely used to locate abnormal areas in failed ICs. Localization is done while the device is activated by a test pattern in a loop. Time Resolved Emission (TRE) has the potential to analyse faults by studying the emission of one area as a function of time. For failure analysis both techniques are valuable to identify where and when abnormal emission events have occurred. At low VDD, using only one or the other emission technique has shown some limitations. A solution, presented here, is to add a NIR PMT detector on an existing light emission microscope. Choice of detectors, performances and implementation are detailed on 120 and 90 nm structures.