Phillip Baraona

Classification and retrieval of reusable components using semantic features

Automated assistance for software component reuse involves supporting retrieval, adaptation and verification of software components. The informality of feature-based software classification schemes is an impediment to formally verifying the reusability of a software component. The use of formal specifications to model and retrieve reusable components alleviates the informality, but the formal reasoning required for retrieval introduces questions of scalability. To provide scalability, current retrieval systems resort to syntactic classification at some level of abstraction, abandoning the semantic information provided by the specification. We propose a methodology that shifts the overhead of formal reasoning from the retrieval to the classification phase of reuse. Software components are classified using semantic features that are derived from their formal specification. Retrieval of functionally similar components can then be accomplished based on the stored feature sets. Formal verification can be applied to precisely determine the reusability of the set of similar components.

VSPEC: A Declarative Requirements Specification Language for VHDL

VHDL allows a designer to describe a digital system by specifying a specific design artifact that implements the desired behavior of the system. However, the operational style used by VHDL forces the designer to make design decisions too early in the design process. In addition, there is no means for specifying non-functional performance constraints such as heat dissipation, propagation delay, clock speed, power consumption and layout area in standard VHDL. Thus, VHDL is not appropriate for high level requirements representation. VSPEC is a Larch interface language for VHDL that solves these problems. VSPEC adds seven clauses to the VHDL entity structure that allow a designer to declaratively describe the data transformation a digital system should perform and performance constraints the system must meet. The designer axiomatically specifies the transformation by defining predicates over entity ports and system state describing input precondition and output postconditions. A constraints section allows the user to specify timing, power, heat, clock speed and layout area constraints. In combination with the architecture declaration, collections of VSPEC specified components can define a high level architecture as interconnected collections of components where requirements of components are known (via a VSPEC description), but implementations are not. This work presents the VSPEC language and associated design methodology.

A Brief Summary of VSPEC

This paper provides an overview of the VSPEC behavioral interface specification language for VHDL. Although operational specification language such as VHDL provide exceptional specification capabilities, at the systems requirements level the operational style is a hindrance. vspec provides VHDL users with a declarative mechanism for defining functional requirements and performance constraints. In the tradition of behavioral interface specification languages, VSPEC adds clauses to the VHDL entity construct allowing axiomatic specification of functional requirements. Because system constraints play an ever increasing role in systems design, VSPEC also provides performance constraint specification capability. This paper presents the basics of VSPEC, its semantics, semantic analysis, and briefly describes current and future applications.

Representing abstract architectures with axiomatic specifications and activation conditions

Evaluating architectural design decisions early in the design process is critical for cost effective design. Formal analysis can provide such evaluation if architectures are defined in a formal way. This paper describes how VSPEC can be used to formally define an architecture during requirements specification. VSPEC is a Larch interface language for VHDL that annotates VHDL entities using the axiomatic style provided by Larch interface languages. Using VHDLs structural definition support, entities described in this manner are connected to form architectural descriptions. Activation conditions over component inputs define when that component must perform its transform. In this paper, we formally define a VSPEC components state and how component states interact in an architecture. A rudimentary formal semantics for component activation is presented and used to define two potential satisfaction criterion.

Extending VHDL to the systems level

Systems engineering is the process of looking at many facets of an emerging design. A systems engineer is required to examine and reconcile many information sources when making high-level design decisions. Although VHDL is an excellent digital system description language, it lacks the flexibility to address all systems-level issues. Digital system behavior and structure are effectively handled, but other facets are not. VSPEC represents one attempt to model other facets in the VHDL framework. It adds functional requirement and performance constraint modeling to the VHDL-based design process. This paper first describes VSPEC and its interaction with VHDL. It argues that VSPEC is an excellent first step towards a systems-level description language. However, other facets are needed to model complete systems. A language structure for representing these facets is proposed and a potential source for a semantic definition is identified.

Using Declarative Specifications and Case-based Planning for System Synthesis

Synthesis of pragmatic systems from high-level specifications requires representation and application of both functional requirements and constraints. This work presents a language for representing requirements and constraints in VHDL design representations and a prototype care-based synthesis system. VSPEC is an annotation language for VHDL developed to support axiomatic representation of requirements for system synthesis. VSPEC descriptions serve as synthesis goals and verification criteria. A prototype case-based synthesis system is also presented that uses VSPEC requirements as goal statements and descriptions of potential solutions. This prototype system demonstrates how synthesis can be performed at the systems level and how constraints can be used to implement a simple concurrent engineering process.

Formal methods at the systems level

This paper presents an attempt at using formal methods as engineering mathematics. We present a Larch interface language for VHDL, called VSPEC, that provides a mechanism for specifying and analyzing systems level requirements. Further, this language supports abstractions and concepts familiar to traditional digital hardware designers. Using VSPEC, it is possible to specify and verify both functional requirements and constraints. Components are specifying using the traditional axiomatic style extended to include performance constraints and activation conditions. Additionally, using VHDLs structural specification features, it is possible to specify and verify abstract architectures formally. The paper opens by describing general characteristics of VSPEC including single component representation and architecture representation. Design rationale are presented to show how VSPEC provides familiar abstractions to the system designer. Finally, annotated examples are presented to demonstrate the language and its expected uses.

VSPEC: a declarative specification methodology for system requirements

Systems engineering of computer-based systems demands explicit representation of functional requirements as well as constraints at each level of design abstraction. However, traditional design representation languages such as VHDL and VERILOG do not support requirements representation independent from implementation. This work presents a axiomatic specification language designed to support requirements representation. VSPEC annotates VHDL entity structures supporting declarative specification of input preconditions, output postconditions and performance constraints as a part of the design representation. The declarative nature of the specification supports requirements definition independent of design representation.