Pierangelo Garino

A VLSI implementation study of a 10 Mbit/s video decoder

Abstract The paper presents the study of a VLSI implementation of a video decoder, targeted for systems with bit-rates up to 10 Mbit/s. Among the features of the decoder are a CCIR 601 4:2:2 full resolution output, the regeneration of a motion compensated prediction using both spatial and temporal interpolation techniques, and an inverse DCT of the coefficients. The paper describes the algorithm of picture encoding that was implemented, gives a global evaluation of the encoding system and presents a detailed proposal for a VLSI implementation of the decoding system.

VLSI-driven system analysis of the motion estimation process in motion picture experts group (MPEG)-2 video

An analysis of the motion estimation system for the MPEG-2 video coding algorithm is reported. With the target of single-chip VLSI implementation, not only the number of operations but mainly the cache size and the memory bandwidth are taken into account as feasibility issues. A multi-minimum motion estimation routine is described but, even if the complexity requirement is strongly reduced, it is not enough to allow large search areas. Finally, a vector tracing approach is proposed to overcome the analyzed drawbacks.

A flexible MIMD pixel processor for high quality MPEG-2 motion and vector processing

This paper will present the design of a MIMD pixel processor, performing motion estimation and other pixel computations for high quality MPEG-2 video coding systems. Unique features of the chip are the implementation of a genetic block matching algorithm, as well as special connections to support a cascaded coding of the video signal minimising the typical impairments produced by such operations.