Pierre Plaza

PLASTIC: Providing lightweight & adaptable service technology for pervasive information & communication

The PLASTIC project adopts and revisits service-oriented computing for Beyond 3rd Generation (B3G) networks, in particular aiming at assisting the development of services targeted at mobile devices. Specifically, PLASTIC introduces the PLASTIC platform to enable robust distributed lightweight services in B3G networking environments through: (a) A development environment for the thorough development of SLA- and resource-aware services, which may be deployed on the various networked nodes, including handheld devices; (b) A service-oriented middleware leveraging multi-radio devices and multi-network environments for applications and services deployed on mobile devices, further enabling context-aware and secure discovery and access to such services; (c) A validation framework enabling off-line and on-line validation of networked services regarding functional and non-functional properties.

Technology for ATM multigigabit/s switches

It is generally accepted that the reasons for selecting ATM as the switching and multiplexing method for B-ISDN are the advantages the bandwidth on demand philosophy offers: flexibility and statistical gain. The main benefit of the throughput improvement that is possible to achieve with link rates of Gb/s in ATM is the exploitation of statistical gain with bursty high peak rate sources. But not only statistical gain justifies the necessity for such advanced technology. High speed ATM switching systems take advantage of the reduction of the number of interface devices (due to multiplexing) and also the number of stages in the ATM switching network, obtaining better figures in the cost/performance ratio. This paper describes an ATM switch that exploits parallelism and segmentation to perform very high speed ATM switching. With this characteristic it is possible to switch more than 2.5 Gb/s per input/output using CMOS and BiCMOS technologies (present implementation) and beyond with more advanced BiCMOS/GaAs.

The BeyWatch Conceptual Model for Demand-Side Management

The BeyWatch project designs, develops and evaluates an innovative, energy-aware and user-centric solution, able to provide intelligent energy monitoring/control and power demand balancing at home/building and larger geographical area level. The focus lies in increasing the use of ICT in power systems. We first provide a brief overview of the concepts involved. After that, we highlight one of the crucial problems of demand side management: striving to attain a balance whereby the system meaningfully influences user behavior / electricity consumption while at the same time avoiding the two extremes of either: (a) putting too much strain on consumers by forcing them to second-guess and obsessively optimize the operation of their appliances or (b) taking over control of their household. We present the BeyWatch Conceptual Model that drove the architecture definition of the BeyWatch platform which solves this conundrum. We finish with a presentation of actual architecture deployed for the trials.

An Optimized eHealth Platfom to Provide Electronic Services over Dynamic Networking Environments

The paper describes how an eHealth platform is being optimized with several enabling technologies for content and services provisioning over new, more complex network topologies. The services that are to be offered must account for dynamic networking environments which include add-hoc networks on the one-hand, and on the other that are to be offered for groups of users, seamlessly connected by using Peer to Peer communications.

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 /spl mu/m technology and the ICM, a 0.7 /spl mu/m CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper.

2.5 Gbit/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are here described, the chip set is composed of: 1) the CMC which is an input/output processor of ATM cells implemented on a BiCMOS 0.7 micron technology; and 2) the ICM, a 0.7 micron CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output.

ICM2 IC: A new ATM switching element for 2.48 Gb/s communications

The ICM2 circuit is part of a new ATM (Asynchronous Transfer Mode) switch core of a new Broad Band ISDN exchange system that can switch at least 2.488 Gb/s. It is being developed by TELEFONICA I+D for the Spanish PTT, TELEFONICA. The circuit was processed with a 0.7 micron CMOS technology, and a first silicon success has been obtained. Its die size is 12.8/spl times/12.1 sqmm and its working frequency is 70 MHz.<<ETX>>

Advanced secure multimedia services for digital homes

Our society is becoming increasingly more IT-oriented, and the images and sounds that reflect our daily life are being stored mainly in a digital form. This digital personal life can be part of the home multimedia contents, and users demand access and possibly share these contents (such as photographs, videos, and music) in an ubiquitous way: from any location and with any device. The purpose of this article is twofold. First, we introduce the Feel@Home system, whose main objective is to enable the previously mentioned vision of an ubiquitous digital personal life. Second, we describe the security architecture of Feel@Home, analyzing the security and privacy requirements that identify which threats and vulnerabilities must be considered, and deriving the security building blocks that can be used to protect both IMS-based and VPN-based solutions.

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC

The design and implementation of an input/output processor for an ATM switch are described. This IC was realized on a 0.7 /spl mu/m BiCMOS technology. To manipulate ATM cells at a frequency of 311 MHz (STM16) at the I/O of the chip, ECL blocks were employed. The core of the chip is composed of CMOS cells that run at a maximum clock speed of 65 MHz. Pure analog blocks were not needed. The CMC is capable of functioning in two different modes: 1. The CM mode, in which 8 bit wide ATM cells are converted to a custom parallel format (microcells). 2. The MC mode, in which microcells are converted into 8 bits wide ATM cells. Two different set of pads were used, ECL and conventional CMOS pads. The circuit complexity is 320 K transistors and its die size is 224 mm/sup 2/. It is encapsulated in a CPGA-319 pin package and dissipates 8.2 watts at 311 MHz.<<ETX>>

ATM traffic shaper: ATS

The design and Implementation of an ATM Traffic Shaper (ATS) is described. This IC was realised on a 0.35 /spl mu/m CMOS technology. The main function of the ATS is the collection of low bit rate traffic to fill a higher bit rate pipe in order to reduce the cost of ATM based services, nowadays mainly influenced by transmission cost. The circuit fits in several ATM system configurations but mainly will be used at the User-Network Interfaces or Network-Network interfaces. The IC was designed with a top-down methodology using as HDL, Verilog. The chip is pad limited and is encapsulated in a 208 PQFP package. The circuit complexity is 38 Kgates and its working frequency is 32 MHz. A circuit prototype was build with FPGAs in order to validate the RTL description.