Pinaki Mazumder

Nanoscale Memristor Device as Synapse in Neuromorphic Systems

A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal-oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.

Digital circuit applications of resonant tunneling devices

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTDs) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBTs) and modulation doped field-effect transistors (MODFETs). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates.

VLSI cell placement techniques

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard cell and macro placement. Five major algorithms for placement are discussed: simulated annealing, force-directed placement, min-cut placement, placement by numerical optimization, and evolution-based placement. The first two classes of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. In each category, the basic algorithm is explained with appropriate examples. Also discussed are the different implementations done by researchers.

Resonant tunneling diodes: models and properties

The resonant tunneling diode (RTD) has been widely studied because of its importance in the field of nanoelectronic science and technology and its potential applications in very high speed/functionality devices and circuits. Even though much progress has been made in this regard, additional work is needed to realize the full potential of RTDs. As research on RTDs continues, we will try in this tutorial review to provide the reader with an overall and succinct picture of where we stand in this exciting field or research and to address the following questions: What makes RTDs so attractive? To what extent can RTDs be modeled for design purposes? What are the required and achievable device properties in terms of digital logic applications? To address these issues, we review the device operational principles, various modeling approaches, and major device properties. Comparisons among the various RTD physical models and major features of RTDs, resonant interband tunneling diodes, and Esaki tunnel diodes are presented. The tutorial and analysis provided in this paper may help the reader in becoming familiar with current research efforts, as well as to examine the important aspects in further RTD developments and their circuit applications.

A genetic approach to standard cell placement using meta-genetic parameter optimization

The genetic algorithm applies transformations on the chromosonal representation of the physical layout. The algorithm works on a set of configurations constituting a constant-size population. The transformations are performed through crossover operators that generate a new configuration assimilating the characteristics of a pair of configurations existing in the current population. Mutation and inversion operators are also used to increase the diversity of the population, and to avoid premature convergence at local optima. Due to the simultaneous optimization of a large population of configurations, there is a logical concurrency in the search of the solution space which makes the genetic algorithm an extremely efficient optimizer. Three efficient crossover techniques are compared, and the algorithm parameters are optimized for the cell-placement problem by using a meta-genetic process. The resulting algorithm was tested against TimberWolf 3.3 on five industrial circuits consisting of 100-800 cells. The results indicate that a placement comparable in quality can be obtained in about the same execution time as TimberWolf, but the genetic algorithm needs to explore 20-50 times fewer configurations than does TimberWolf. >

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

Compact multiple-valued multiplexers using negative differential resistance devices

Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal values and the output line corresponds to the selected input. Any four-valued logic function can be implemented using only four-valued multiplexers (also known as T-gates), and this T-gate uses just 13 devices (transistors) as compared to 44 devices in CMOS. The design of the T-gate was done using a combination of resonant tunneling diodes (RTDs) and heterojunction bipolar transistors (HBTs) with the folded I-V characteristic (NDR characteristic) of the RTDs providing the compact logic implementation and the HBTs providing the gain and isolation. The application of the same design principles to the design of T-gates using other NDR devices such as resonant tunneling hot electron transistors (RHETs) and resonant tunneling bipolar transistors (RTBTs) is also demonstrated.

CMOS and Memristor-Based Neural Network Design for Position Detection

Most hardware neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights two basic learning rules/behavior: winner-take-all (WTA) and spike-timing-dependent plasticity (STDP). It also gives a design example implementing WTA combined with STDP in a position detector. A complementary metal-oxide-semiconductor (CMOS) and a memristor-MOS technology (MMOST) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout were done in 130-nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes area, 55-W max power, and requires a 3-dB SNR. On the other hand, the MMOST design consumes , 15-W max power, and requires a 4.8-dB SNR. There is a potential to improve upon analog computing with the adoption of MMOST designs.

Memristor-Based Cellular Nonlinear/Neural Network: Design, Analysis, and Applications

Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

Tunneling devices and applications in high functionality/speed digital circuits

Abstract Tunneling phenomena can be used to realize devices with unique I-V characteristics (negative differential resistance) which can be employed to design various types of digital circuits with a significantly lower number of transistors, extremely fast switching speeds, very low power consumption and pipelining capability at the basic gate level (nanopipelining) which results in higher system throughput. In this article, we will present the basic properties of various types of devices which have been proposed for these applications including resonant tunneling diodes (RTDs), Esaki tunnel diodes (ETDs), and various types of transistors including resonant hot electron transistors (RHETs) and tunneling bipolar transistors (TBTs). We will also compare the anticipated performance of various types of logic gates and digital circuit implementations utilizing these devices with conventional CMOS circuits.