Pingye Xu

High Channel Mobility 4H-SiC MOSFETs by Antimony Counter-Doping

Channel mobility of >100 cm2V-1s-1 has been obtained on enhancement mode 4H-SiC MOSFETs using an antimony (Sb) doped surface channel in conjunction with nitric oxide (NO) postoxidation annealing. Temperature dependence of the channel mobility indicates that Sb, being an n-type dopant, reduces the surface electric field while the NO anneal reduces the interface trap density, thereby improving the channel mobility. This letter highlights the importance of semiconductor/dielectric materials processes that reduce the transverse surface electric field for improved channel mobility in 4H-SiC MOSFETs.

Reduced-Loss Ink-Jet Printed Flexible CPW With Copper Coating

Electroplating copper onto ink-jet printed silver coplanar waveguide (CPW) significantly reduces the insertion loss and can improve return loss. The structures are fabricated on flexible polyimide substrates using ink-jet printing and low-temperature curing. Copper-coated silver CPW exhibits good adhesion and flexibility and the RF and microwave performance is minimally affected by bending.

Fabrication and Characterization of Double Helix Structures for Compliant and Reworkable Electrical Interconnects

Microelectromechanical systems (MEMS)-type double helix chip-level electrical interconnect structures are fabricated and characterized in this paper. Due to their springlike structure, double helix interconnects have the potential to provide large mechanical compliance to compensate for nonidealities, such as nonplanarity and thermal expansion mismatch between silicon chips and substrates. A double helix configuration provides for structures with a high volumetric density of conductor for enhanced current carrying capability. The fabrication process is compatible with wafer-level fabrication and packaging. Instead of using solder to form semipermanent interconnections, the double helix interconnects use pressure to make electrical connection and provide sufficiently low resistance (~35 ± 15 mΩ). Large arrays of double helix structures have been fabricated and characterized with excellent yield. The mechanical and electrical models of the structures are presented. Reworkability tests were performed and the structures show a consistent resistance over 50 remating cycles.

Solution-Based Fabrication of Carbon Nanotube Bumps for Flip-Chip Interconnects

A reliable solution-based process to fabricate thick carbon nanotube (CNT) bumps has been developed and is presented in this paper. In contrast to other work of this nature, the process we have developed is capable of fabricating thick and densely packed CNT structures at room temperature with relatively high resolution and controllable film thickness or bump height. CNT structures fabricated using the developed method may find use in sensors or electrical interconnect applications. Raman spectroscopy was used to characterize the fabricated CNT bumps, verifying the CNTs are negligibly affected by the fabrication process. To study the potential application of these CNT bumps for flip-chip interconnections, we examined the deformation of the CNT bumps after flip-chip bonding and performed electrical characterization. The CNT bump interconnects display linear I-V curve with an average resistance of approximately 484 mΩ for a bump with 200 μm diameter and height of 12 μm. Temperature-dependent measurements indicate that fluctuation-induced tunneling (FIT) is the most likely electrical conduction mechanism in the CNT bumps.

Electrical characteristics and density of states of thin-film transistors based on sol-gel derived ZnO channel layers with different annealing temperatures

We report on the fabrication and electrical characterization of bottom gate thin-film transistors (TFTs) based on a sol-gel derived ZnO channel layer. The effect of annealing of ZnO active channel layers on the electrical characteristics of the ZnO TFTs was systematically investigated. Photoluminescence (PL) spectra indicate that the crystal quality of the ZnO improves with increasing annealing temperature. Both the device turn-on voltage (Von) and threshold voltage (VT) shift to a positive voltage with increasing annealing temperature. As the annealing temperature is increased, both the subthreshold slope and the interfacial defect density (Dit) decrease. The field effect mobility (μFET) increases with annealing temperature, peaking at 800 °C and decreases upon further temperature increase. An improvement in transfer and output characteristics was observed with increasing annealing temperature. However, when the annealing temperature reaches 900 °C, the TFTs demonstrate a large degradation in both transf...

Flip-chip interconnects based on solution deposited carbon nanotube bumps

A solution based fabrication process of carbon nanotube (CNT) bump interconnects is proposed. In comparison to CVD growth of CNT which requires high process temperature, the proposed process has the advantage of being capable to fabricate CNT bumps at room temperature with relatively high resolution and adjustable bump height. The average resistance of the fabricated CNT bumps was measured to be 904 mΩ, comparable to the resistance of the transferred CVD grown CNT bumps.

Flip chip based on compliant double helix interconnect for high frequency applications

Compliant interconnects are a viable solution for coefficient of thermal expansion (CTE) mismatch failures and it is therefore important to understand their performance at high frequency. In this work, we present double helix shaped compliant interconnects that are designed and fabricated on top of a coplanar waveguide (CPW) test structure followed by flip chip bonding. The high frequency performance of compliant double helix interconnect is simulated and measured. The measured insertion and reflection loss were less than -0.6 dB and -15 dB up to 50 GHz, respectively.

Solution-Deposited Carbon Nanotube Flip Chip Interconnect for High-Frequency Applications

A coplanar waveguide (CPW) structure with carbon nanotube bumps as flip chip interconnects is presented. The carbon nanotube (CNT) interconnects are fabricated using a solution-based method. This work shows the feasibility of using solution-deposited CNTs as flip chip interconnects and presents their high frequency characteristics in comparison to similarly-sized gold interconnects. The solution-deposited CNT interconnects have similar resistance to transferred CNT bumps grown by chemical vapor deposition. The fabricated CNT bumps are well shaped and have an average dc resistance of 970 mΩ ( 150 μm in diameter and 10 μm in height). High frequency characterization was carried out up to 40 GHz. The return loss is better than 15 dB and the insertion loss of the CNT interconnect is 0.3 dB higher than conventional gold bump interconnects per transition.