Piotr Dudek

Neuromorphic silicon neuron circuits

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities

This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of operation: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global operations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 × 22 proof-of-concept array has been manufactured in 0.35 μm CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably compares with other digital and analog vision chips. The results of low- and medium-level image processing on the chip are presented.

A Fast Self-Tuning Background Subtraction Algorithm

In this paper, a fast pixel-level adapting background detection algorithm is presented. The proposed background model records not only each pixels historical background values, but also estimates the efficacies of these values, based on the occurrence statistics. It is therefore capable of removing the least useful background values from the background model, selectively adapting to background changes with different timescales, and restraining the generation of ghosts. A further control process adjusts the individual decision threshold for each pixel, and reduces high frequency temporal noise, based on a measure of classification uncertainty in each pixel. Evaluation results based on the ChangeDetection.net database are presented in this paper. The results indicate that the proposed algorithm outperforms the majority of earlier state-of-the-art algorithms not only in terms of accuracy, but also in terms of processing speed.

A CMOS general-purpose sampled-data analog processing element

This work presents the architecture and implementation of an analog processor, which in a way akin to a digital microprocessor, embodies a physical model of the universal Turing machine. The analog microprocessor (A/spl mu/P) executes software programs, while nevertheless operating on analog sampled data values. This enables the design of mixed-mode systems which retain the speed/area/power advantages of the analog signal processing paradigm, while being fully programmable general-purpose systems. A proof-of-concept integrated circuit has been implemented in 0.8-/spl mu/m CMOS technology, using switched-current techniques. Experimental results from fabricated chips are presented and examples of the application of the A/spl mu/Ps in image processing are given.

Integrated circuit implementation of a cortical neuron

This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 mum CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks.

An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays

Massively parallel processor-per-pixel single-instruction multiple data arrays are being successfully used for early vision applications in smart sensor systems; however, they are inherently inefficient when executing algorithms involving propagation of binary signals, such as the geodesic reconstruction. Yet, these algorithms, at the interface between pixel-level and object-level image processing, should be implemented on the vision chip to facilitate data reduction at the sensor level. A cellular asynchronous network is presented in this paper, which can be used to execute binary propagation operations. The proposed circuit is optimized in terms of speed and power consumption. In 0.35-/spl mu/m technology, the simulated propagation speed is 0.18 ns per pixel and the total energy expended per propagation is 0.37 pJ per cell. In this brief, implementation issues are discussed and simulation results including image processing examples are presented.

Implementation of SIMD vision chip with 128/spl times/128 array of analogue processing elements

This paper presents the latest implementation of the SIMD current-mode analogue matrix processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35 micrometre CMOS technology and comprises a 128/spl times/128 general-purpose programmable processor-per-pixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the analogue processing element is discussed and the design of control-signal drivers and readout circuitry is overviewed.

APRON: a cellular processor array simulation and hardware design tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.