Piotr Penkala

Distributed Collaborative Design of a Mixed-Signal IP Component

A novel approach for enabling distributed design of heterogeneous systems and components is introduced in the paper. It integrates concepts of visual knowledge modeling, engineering workflows, collaborative workspaces, design task patterns, and remote tool invocation. These concepts are supported by a collaboration platform - a result of the EU FP6 project MAPPER. The design approach and the supporting collaboration platform have been applied in the USB2 OTG PHY IP core design that required collaboration among two dispersed SMEs. Mixed-signal USB design challenges, distributed design flow, requirements for enhanced EDA support, and selected design tasks enabled by the collaboration platform have been discussed. Finally, advantages and constraints of the design approach have been pointed to.

Web Services-Based Collaborative System for Distributed Engineering

• Collaborative engineering for distributed product development • Challenges in collaborative design• MAPPER project objectives and approach• MAPPER collaborative infrastructure• Requirements for distributed tool integration• TRMS - Tool Registration and Management Services• New TRMS architecture• Deployment of TRMS• Conclusions

Distributed collaborative design of IP components in the TRMS environment

A methodology, an application scenario and a new system enabling collaborative distributed design have been presented. The system based on Tool Registration and Management Services (TRMS) constitutes the core of the engineering collaborative infrastructure that has been deployed in the distributed design of intellectual property (IP) components. The system assures information security (including user authorization, data and transfer encrypting), communication through firewalls, remote administration of users and tools, and some support for distributed inter-organization workflows.

Collaborative Infrastructure for Distance-Spanning Concurrent Engineering

Design of complex Systems-on-a-Chip requires often integration of large teams of engineers who work in remote locations. Seamless and secure integration of distant tools across different organization over the Internet is still one of major challenges that obstacles efficient engineering collaboration. The paper explains the main element of the advanced collaborative infrastructure that supports integration of distributed engineering tools. It constitutes TRMS (Tool Registration and Management Services) which are scalable, easily accessible, secure, and available on different platforms due to their implementation in Java. Requirements on TRMS, its architecture and functionality, as well as conclusions stemming from first deployments are presented.

Modular FPGA-based hardware platform for emulation

The paper presents logic concepts of scalable architecture of a system for emulation purposes along with dedicated, underlying FPGA-based board modules as an implementation platform. These modules provide scalability of emulation system and support full system functionality. This article also presents an analysis of feasibility of the scalable system based on a hybrid-structure. The system consists of dedicated hardware modules and third-party, easy-to-get evaluation boards to provide a cheap solution with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, connectors etc. the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. The paper discusses the use of this system throughout the different emulation modes as well as explains problems common to modern logic gate arrays. The article presents performance achievements of the implemented communication channel to the host and discusses the architectural features affecting system construction and efficiency.

Verification approach based on emulation technology

The paper presents a scalable architecture for fast emulation of Systems-on-Chip. It is implemented on a dedicated modular FPGA-based hardware platform. This verification eco-system presents a new approach to improve efficiency of the verification process through hardware-based acceleration of tests. The system consists of dedicated hardware modules and third-party; easy-to-get evaluation boards to provide an affordable solution for SMEs with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, and connectors, the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. It provides a debug capability which enables quick identification and elimination of implementation bugs. The paper also reports on the use of the emulation environment in FPGA-in-the-Loop simulation. This solution may be applied to a broad range of applications.