Po-An Chen

Effects of antimony and arsenic ion implantation on high performance of ultra high voltage device

This paper presents a low cost innovative dual channel engineering to simulate the effects of arsenic and antimony implantation over breakdown voltage and on state resistance of an Ultra High Voltage (UHV) device. There are many devices in market with multiple conduction paths, but all these devices use high energy implants. But we have used a low cost and low energy implant over P-top to form an extra conduction path. Optimizations are done to obtain high breakdown voltage and lower Ron by varying the P-top and Ntop over P-top. We demonstrate interface charge analysis for both Antimony and Arsenic implantation over P-top and also we investigate the effect of N-top implantation before and after NDrift diffusion on breakdown voltage.

Conventional 100V UMOS technology with deeper P+ to improve Ids

An innovative and improved UMOSFET device with low specific on-resistance maintain desired breakdown voltage up to 100V. In this proposed device, p-pillar under the p+ region UMOS structure has been developed and successfully simulated by using 2D simulation. The proposed structure can reduce the electric field near the trench gate UMOSFET. The trench gate with p-pillar increase the drift region doping concentration can reduce the specific on-resistance 1.2 mΩ-mm2 while maintaining a breakdown voltage of above 100 volts. This proposed innovative structure can improve the 60% on state breakdown voltage with good Ids current level. The proposed structure conventional trench gate UMOS can also achieve better UIS performance and HCI Reliability.

Design for hot-carrier reliability of HV UMOS

An innovative and improved UMOS device structure, with gate oxide 900 to 1500A, breakdown voltage 40 to 100V, robust to hot carrier injection (HCI) stress is proposed. We demonstrate and report the effect of p-type and n-type doping in gate oxide and poly-gate region can improve HCI performance significantly. The UMOSFETs HCI, response to doping in the gate oxide and poly-gate is been studied.

Performance improvement for drain expansion and Quasi Saturation by using Vertical RESURF in UMOSFET

In this work, a trench power MOSFET (UMOS) with vertical RESURF is investigated. And the influence of some key parameters on UMOS static performances are simulated and analyzed by TCAD-Process. The proposed RESURF conventional trench gate UMOS is able to achieve better UIS performance while maintaining a specific low on state-resistance with breakdown voltage over 100 Volts. Here we are proposing a new Vertical RESURF concept by using Arsenic and phosphorus implantation. The simulation results we have shown that Arsenic and Phosphorus vertical RESURF concept are important to improve the drain expansion problem and the Quasi Saturation effect along with maintaining breakdown voltage and on-state resistance. This proposed concept improves the Ids.

Study on Poly-Buffered LOCOS isolation for BCD application

In Complementary Metal Oxide Semiconductor (CMOS) process, isolation is the key and it has got more influence on the device performance. The most advanced process is using Shallow trench isolation (STI) technology, but for small geometry processes using STI technology will be very difficult because of severe HCI (Hot Carrier Injection) problem and need to have new advanced equipment for using STI technology. So many factories still using Local Oxidation of Silicon (LOCOS) isolation for small geometry applications like nano-devices. LOCOS isolation has a problem because of its birds beak will occupy big area and causes leakage path. Using Poly-Buffer in the LOCOS isolation will reduce the birds beak around 40% and hence CMOS integration process improves product yield and performance will be drastically improved. Feature of the model using Poly-Buffered LOCOS (PBLOCOS) is very similar and very easy than using basic LOCOS process. Sometime PBLOCOS Isolation will be more useable than STI technology.

Optimization of NLDMOS structure for higher breakdown voltage and lower On-Resistance

In this work, high voltage NLDMOS performance in terms of high blocking voltage and On-Resistance have been investigated. In order to obtain the optimum electrical performance several key factors have been optimized such as linearity of HVNW profile, drift length and source field plate. Linear HVNW profile is obtained by linearity of HVNW mask. NLDMOS having blocking voltage of 100 V-300 V and lower On-resistance is developed based on 0.35um BCD Technology with less manufacturing cost. It is investigated that NLDMOS has poor performance over blocking voltage of 300V.

Study of different spatial charge trapping distribution effect on off-state degradation at elevated temperature in power LDMOS

Different spatial charge trapping distribution effect on off-state degradation in power LDMOS was studied. Electron trapping phenomena is thermally grown in silicon dioxide (SiO2). Due to charge can be trapped in the oxide, it can make structural defects, oxidation-induced defects, impurities, or other defects caused by Si-O-bond breaking process. This process can increase leakage current and cause off-state breakdown degradation. Many research already discussed about this mechanism, but not too much described about the distribution of charge trap into SiO2. In this paper, the distribution of charge trap in SiO2 was studied in three different spatial charge distribution: Uniform, Gaussian, and Exponential using Sentaurus TCAD simulation software. This phenomena also studied at elevated temperature 150°C compare with room temperature.

Ron improvement with duplex conduction channel in UHV device

This paper presents a low cost innovative duplex channel engineering to simulate and improve specific on-state resistance (Ron) of an Ultra high voltage (UHV) device without compromising on breakdown voltage. In manufacturing of UHV device, tradeoff between on state resistance and breakdown voltage is always present. But with our process design we are able to improve Ron by 15-20% without compromising the breakdown voltage. There are many devices in market with multiple conduction paths, but all these devices use high energy implants. These high energy implants are costly and accuracy of high dose/energy implants is less when compared to low dose/energy implants. Hence we have used a low cost and low energy implants for P-top and N-top to form an extra conduction path. Optimizations are done to obtain high breakdown voltage and lower Ron by varying the P-top and N-top over P-top. As reliability of device is important, we have investigated the interface charge effect on breakdown and the device sustain breakdown voltage for interface charge of 1.5e11. ESD test is also conducted and this structure can pass 4KeV.