Po-Hsun Wu

1-D Cell Generation With Printability Enhancement

As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.

Placement optimization of flexible TFT circuits with mechanical strain and temperature consideration

Mobility is the primary device parameter affecting circuit performance in flexible thin-film transistor (TFT) technologies, and is particularly sensitive to the change of mechanical strain and temperature. However, existing algorithms only consider the impact of mechanical strain in cell placement of flexible TFT circuits. Without taking temperature into consideration, mobility may be dramatically decreased which leads to circuit performance degradation. This article presents the first work to minimize the mobility variation caused by the change of both mechanical strain and temperature. Experimental results show that the proposed algorithms can effectively and efficiently reduce the increasing critical path delay.

A topology-based ECO routing methodology for mask cost minimization

Although several Engineering Change Order (ECO) routers had been proposed to obtain a routing solution based on different design objectives, mask re-spin cost still cannot be effectively reduced because the ECO routing problem is handled in a sequential manner. This paper presents a three-stage ECO routing flow which can simultaneously route all ECO nets while considering routing layer minimization. Experimental results demonstrate that our proposed ECO routing flow can effectively reduce the number of changed masks with only negligible wirelength and via overhead.

Bus-driven floorplanning with thermal consideration

As the increasing number of buses in multi-core SoC designs, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, these proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots, which result in high chip temperature, on the chip. In this paper, a thermal-driven bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles, which are the thermal distribution of each module, is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature.

Thermal-aware bus-driven floorplanning

As the number of buses in multi-core SoC designs increase, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, those proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots which result in high chip temperature on the chip. In this paper, a thermal-aware bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles which are the thermal distribution of each module is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplan-ner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids — Placement and Routing General Terms: Algorithms, Design

Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.

A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration

Mobility is the key device parameter to affect circuit performance in flexible thin-film transistor (TFT) technologies, and it is very sensitive to the change of mechanical strain and temperature. However, existing algorithms only consider the impact of mechanical strain in cell placement of flexible TFT circuit. Without taking temperature into consideration, mobility may be dramatically decreased which leads to circuit performance degradation. This paper presents the first work to reduce the mobility influence caused by the change of both mechanical strain and temperature. Experimental results show that the proposed algorithms can effectively reduce the chip temperature and the influence caused by mobility variation.

Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes even more severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the FinFET technology to analog circuit design, the variation of drain currents can destroy current-ratio matching among transistors and degrade circuit performance. In this article, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer.

Triangle-based process hotspot classification with dummification in EUVL

As technology node advances, Extreme Ultraviolet Lithography (EUVL) is regarded as the most promising technology for improving the lithographic printability. However, there are still several challenges in EUVL like the most critical flare effect that causes patterning distortions. As a result, dummy fills are added to a layout (i.e., dummification) to compensate the flare effect. Although dummy fills are used to alleviate the flare effect, process hotspots still cannot be fully eliminated and are essential to be detected in the early design stages. Pattern matching is one of the most popular and widely-used technique to detect the process hotspots. However, existing pattern-matching-based algorithms may not effectively detect all process hotspots under the consideration of dummification. In this paper, we propose a two-stage triangle-based algorithm for process hotspot classification while considering the impact of dummification in EUVL. Experimental results show that our proposed algorithm is very effective and efficient compared with the state-of-the-art process hotspot classification algorithm.

Bus-driven floorplanning with bus pin assignment and deviation minimization

As the number of buses increase substantially in multi-core SoC designs, the bus planning problem has become the dominant factor in determining the performance and power consumption of SoC designs. To cope with the bus planning problem, it is desirable to consider this issue in early floorplanning stage. Recently, the bus-driven floorplanning problem has attracted much attention in the literature. However, current algorithms adopt an over-simplified formulation which ignores the orientation of the bus pin, the chip performance may be deteriorated. In this paper, we propose the bus-driven floorplanning algorithm that fully considers the impact of the bus pin. By fully utilizing the position and orientation of the bus pin, bus bendings are not restricted to occur at the module of the same bus, then more flexible bus shape is obtained. With more flexibility on the bus shape, the size of the solution space is increased and a better bus-driven floorplanning solution can be obtained. In conference version, compared with the bus-driven floorplanner [6], experimental results show that our algorithm performs better in runtime by 3.5x, bus wirelength by 1.4x, and deadspace by 1.2x, respectively. In this paper, we improve the algorithm in [11] to obtain better driver-load delay variation among all bus bits.