Poona Bahrebar

The Hamiltonian-based odd-even turn model for maximally adaptive routing in 2D mesh networks-on-chip

Display Omitted A highly adaptive routing method is proposed for wormhole-switched 2D mesh networks.The degree of adaptiveness is maximized by minimizing the number of prohibited turns.The deadlock-freedom is guaranteed without adding virtual channels.The proposed method is minimal and can be used for unicast/multicast routing.The number of hotspots is diminished and the traffic distribution is efficient. Networks-on-Chip (NoCs) have emerged as a promising solution for the communication crisis in todays high-performance Multi-Processor System-on-Chip (MPSoC) architectures. Routing methods have a prominent role in taking advantage of the potential benefits offered by NoCs. As a result, designing high-performance and efficient routing algorithms is highly desirable. In this paper, the Hamiltonian-based Odd-Even (HOE) turn model is proposed for both unicast and multicast routing in wormhole-switched 2D mesh networks. HOE is able to maximize the degree of adaptiveness by minimizing the number of prohibited turns, such that the algorithm remains deadlock-free without adding virtual channels. By increasing the number of alternative minimal paths, the hotspots are less likely to be created and the traffic is efficiently distributed throughout the network. The simulation results in terms of latency and power consumption indicate the better performance of the proposed method in comparison with the existing routing methods.

Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip

Networks-on-Chip (NoCs) are becoming more susceptible to faults due to the increasing density in the VLSI circuits. As a result, designing reliable and efficient routing methods is highly desirable. Most of the existing fault-tolerant routing techniques use nonminimal paths to reroute the packets around the faulty regions. Using these approaches, the network performance degrades drastically not only by taking unnecessary longer paths, but also by creating hotspots around the faults. Moreover, they are designed statically and cannot adapt to the dynamic traffic distribution in the network. In this paper, a reconfigurable and fault-tolerant routing method is proposed which is designed based on the Abacus Turn Model (AbTM). The presented deadlock-free routing technique is dynamically tuned based on the location of faults and congestion in the network. Thus, it is able to tolerate all single router failures without exploiting virtual channels. Moreover, it can grant full adaptiveness to the hotspot regions of the network. Using this scheme, the rerouting is minimized by forwarding the packets through the available shortest paths. This efficiency makes the proposed method a powerful asset for reliable routing in NoCs.

Improving hamiltonian-based routing methods for on-chip networks: A turn model approach

The overall performance of Multi-Processor System-on-Chip (MPSoC) platforms depends highly on the efficient communication among their cores in the Network-on-Chip (NoC). Routing algorithms are responsible for the on-chip communication and traffic distribution through the network. Hence, designing efficient and high-performance routing algorithms is of significant importance. In this paper, a deadlock-free and highly adaptive path-based routing method is proposed without using virtual channels. This method strives to exploit the maximum number of minimal paths between any source and destination pair. The simulation results in terms of performance and power consumption demonstrate that the proposed method significantly outperforms the other adaptive and non-adaptive schemes. This efficiency is achieved by reducing the number of hotspots and smoothly distributing the traffic across the network.

Adaptive multicast routing method for 3D mesh-based Networks-on-Chip

The amalgamation of 3D VLSI technology and Networks-on-Chip (NoCs) offers a promising architectural platform for the future Multi-Processor Systems-on-Chip (MPSoCs). Since multicast communication is frequently exploited in such systems, it is highly desirable to design NoC-based routing methods that support multicast. In this paper, a highly adaptive and deadlock-free multicast routing method is proposed for 3D mesh-based NoCs without using virtual channels. Unlike conventional turn models which prohibit certain turns to avoid deadlock, the proposed scheme restricts the locations where certain turns can take place to provide a more even degree of routing adaptiveness. Moreover, different sets of rules are employed for different layers of the NoC to decrease the likelihood of congestion in the network. The simulation results demonstrate the efficiency of the proposed method due to a balanced traffic distribution across the network.

Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method

The incorporation of the third dimension in the design of Networks-on-Chip (NoCs) provides a major performance improvement for Chip Multi-Processors (CMPs). Since multicast communication is necessary for parallelization, it is of significant importance to design routing methods that support multicast. The partitioning strategy has a major impact on the efficiency of the multicast routing method. The existing 3D partitioning methods are designed oblivious to the coherent traffic distribution in CMP networks. In this paper, we propose a novel partitioning method which is compatible with the locality of the traffic distribution across the network. By increasing the parallelism through eliminating the unnecessary long paths, a high performance structure is provided which is a valuable asset for CMPs. The experimental results indicate an average gain of 18% in performance and 4% in power consumption near the saturation points by exploiting the proposed partitioning strategy.

Hamiltonian Path Strategy for Deadlock-Free and Adaptive Routing in Diametrical 2D Mesh NoCs

The overall performance of Network-on-Chip (NoC) is strongly affected by the efficiency of the on-chip routing algorithm. Among the factors associated with the design of a high-performance routing method, adaptivity is an important one. Moreover, deadlock-and live lock-freedom are necessary for a functional routing method. Despite the advantages that the diametrical mesh can bring to NoCs compared with the classical mesh topology, the literature records little research efforts to design pertinent routing methods for such networks. Using the available routing algorithms, the network performance degrades drastically not only due to the deterministic paths, but also to the deadlocks created between the packets. In this paper, we take advantage of the Hamiltonian routing strategy to adaptively route the packets through deadlock-free paths in a diametrical 2D mesh network. The simulation results demonstrate the efficiency of the proposed approach in decreasing the likelihood of congestion and smoothly distributing the traffic across the network.

The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networks

Optimization of multiprocessor systems relies heavily on the efficient design of on-chip routing algorithms. Adaptive routing appears to have an extremely significant role in the performance of the Networks-on-Chip. In this paper, a deadlock-free and highly adaptive minimal routing method (HOE) is proposed. Although the Hamiltonian Adaptive Multicast Unicast Model (HAMUM) is able to support a high degree of adaptiveness, it cannot exploit some of the potential alternative paths in routing. By prohibiting the minimum number of turns, our proposed method strives to find the maximum number of alternative paths between each pair of source and destination nodes, without using virtual channels. HOE has also been applied to the Column-Path (CP) routing algorithm to improve its characteristics. The simulation results validate the flexibility of our approach in choosing the appropriate routing path depending on the congestion condition of the network. The better performance of the proposed method is due to its higher degree of adaptiveness which results in less vulnerability to nonuniform factors and a better traffic distribution all over the network.

Making Communication a First-Class Citizen in Multicore Partitioning

Computation-intensive image processing applications need to be implemented on multicore architectures. If they are to be executed efficiently on such platforms, the underlying data and/or functions should be partitioned and distributed among the processors. The optimal partitioning approach is the one which aims to minimize the inter-processor communication while maximizing the load balance. With the continuously increasing number of cores which exacerbates the demand for more complex memory hierarchies, non-uniform memory access, etc., on-chip communication has gained a significant role in taking advantage of the multicore chips. Therefore, making partitioning decisions just based on conventional performance results and without communication profiling is suboptimal. In this paper, we explore the behavior of a mesh decoder as a case study in terms of communication and computation, and propose models that allow early prediction of the applications behavior. Using these models, profiling the application for all of the input samples is not necessary anymore. As a result, communication- and computation-aware parallelization could be performed faster and easier.

Adaptive routing in MPSoCs using an efficient path-based method

On-chip communication appears to have an extremely significant role in taking advantage of the inherent parallelization offered by the MPSoCs. If interconnection networks are to be used efficiently in such platforms, designing high-performance routing algorithms is inevitable. In this paper, a deadlock-free and highly adaptive multicast/unicast routing method is presented based on the Hamiltonian routing model. This method strives for a high degree of adaptiveness by finding the maximum number of minimal paths between each pair of source and destination. Experimental results demonstrate that the proposed method significantly outperforms the other adaptive and non-adaptive algorithms in terms of latency and power consumption. This efficiency is achieved by alleviating the number of hotspots through a better traffic distribution all over the network.

Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs

With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient NoCs is of significant importance. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. Moreover, they cannot adapt to the dynamic traffic distribution in the network. Considering the increasing demands for real-time systems, the necessity for designing reconfigurable and robust NoCs is even more pronounced. In this paper, a dynamically reconfigurable technique is proposed to address fault-tolerance and minimal routing in mesh NoCs. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.