Prabhakar Goel

Test Generation Costs Analysis and Projections

Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault simulation costs, and minimum test pattern generation costs for LSSD logic structures. The formulae are significant in projecting growth trends for test volumes and various test generation costs with increasing gate count G. Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures. Such LSSD structures are referred to as “coupled” structures. Based on empirical observation that the number of latches in an LSSD logic structure is proportional to the gate count G, it is shown that the logic test time for coupled structures grows as G2. It is also shown that (i) parallel fault simulation costs grow as G3, (ii) deductive fault simulation costs grow as G2, and (iii) the minimum test pattern generation costs grow as G2. Based on these projections some future testing problems become apparent.

Electronic Chip-In-Place Test

Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips. Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.

PODEM-X: An Automatic Test Generation System for VLSI Logic Structures

Multiple test generation algorithms and techniques described in this paper have been integrated into a unified system which has successfully produced tests for unpartitioned LSSD logic structures of up to 50,000 logic gates. The design concepts behind the creation of a unified system are presented, as are actual results obtained on large logic structures. System usability was significantly enhanced by the same concepts that facilitated the integration of multiple algorithms and techniques.

Comments on "Multiple Fault Detection in Combinational Networks"

Some comments on a recent contribution on multiple fault detection using test sets for single fault detection are presented. A counter example that shows some defects in generalizing from a tree to an arbitrary network are also included.