Pradeep Dixit

Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)

Through-Silicon Vias (TSVs) have garnered a lot of interest in recent years because TSV is a key enabling technology for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP). There has been significant effort in TSV fabrication and electrical design. However, considerably less work has been done on thermo-mechanical analysis and mechanical design of these structures. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the conducting material in the vias, thermo-mechanical reliability is a major concern. This paper uses Finite-Element (FE) models and X-ray diffraction (XRD) experiments for the thermo-mechanical analysis of TSVs. Two-dimensional thermo-mechanical Finite-element models have been built to analyze the stress/strain distribution in the TSV structures, and the models show that large stress gradients and plastic deformation exist near the corner of electroplated Cu pads. The stress results from the finite-element models have been compared against XRD experimental data. A fracture mechanics analysis has also been performed, and the fracture analysis shows that Cu/SiO2 interfacial cracks and SiO2 cohesive cracks are more likely to initiate and propagate at those corner locations.

Through-wafer electroplated copper interconnect with ultrafine grains and high density of nanotwins

High aspect ratio (∼15) and ultrafine pitch (∼35μm) through-wafer copper interconnection columns were fabricated by aspect-ratio-dependent electroplating. By controlling the process parameters, ultrafine copper grains with nanoscale twins (twin lamellar width ∼20nm) were obtained in the copper columns. Transmission electron microscope reveals that the density of these nanotwins depends on the location along the length of the columns. The highest twin density was achieved at the bottom of the column where the electroplating starts. The presence of higher density of the nanotwins yields significant higher hardness (∼2.4GPa) than that with lower twin density (∼1.8GPa). The electrical conductivity of the electroplated copper (2.2μΩcm) is retained comparable to the pure copper.

Mechanical and microstructural characterization of high aspect ratio through-wafer electroplated copper interconnects

In this paper we present the mechanical and microstructural characterization results of through-wafer electroplated copper interconnects. Copper was deposited in very high aspect ratio (~15), narrow (15 µm) through-vias in silicon, which were earlier created by deep reactive ion etching. The two critical mechanical properties, i.e. hardness and modulus of elasticity, and the microstructure of the electroplated copper interconnect were determined by nanoindentation, atomic force microscope and x-ray diffraction techniques. A location-dependent hardness characteristic was shown along the length of electroplated copper interconnects. The modulus and the hardness of copper interconnects at the bottom segment (124 GPa and 1.8 GPa) were found to be higher than those at the top segment (116 GPa and 1.1 GPa). The reason behind these variable hardness values in the copper interconnect was due to the different grain sizes and the microstructure in the electroplated copper. These varying grain sizes were caused by the incremental current densities used during electrodeposition. The thermal strain, generated due to the coefficient of thermal expansion mismatch, was measured by the digital image speckle correlation technique. From the results, the thermal strain in the Y-direction was found to be more dominant than that in the X-direction. The grain sizes and the preferred texture orientation in the electroplated copper were characterized by the x-ray diffraction technique.

Numerical and Experimental Investigation of Thermomechanical Deformation in High-Aspect-Ratio Electroplated Through-Silicon Vias

In this paper we present the numerical and experimental analysis of thermomechanical deformation in high-aspect-ratio copper electroplated through-silicon vias (TSVs), which were fabricated by deep reactive ion etching, thermal oxidation, and bottom-up electroplating processes. Later, these TSVs were subjected to thermal cyclic loading of 25-125°C. Due to the significant mismatch in the coefficients of thermal expansion of silicon and copper, thermomechanical stress was generated at the copper-silicon interface. Detailed investigation of this stress is of prime importance as it is one of the main root-causes behind the crack formation and dielectric delamination at the interface. A three-dimensional finite element model of the copper-filled TSVs was built and simulation was performed to predict the theoretical distribution of thermomechanical deformation. A noncontact digital image speckle correlation technique was used for the in situ measurement of the thermal deformation and the thermomechanical stress. Thermomechanical shear strain at the copper-silicon oxide-silicon interface was found to be the significant deformation mode in these TSVs.

Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating

In this paper, we report the fabrication of high aspect ratio, highly dense, very fine pitch on-chip copper-pillar-based interconnects for advanced packaging applications. Photoresist molds up to a thickness of 80 µm and having feature sizes as small as 5 µm were fabricated using multi-step coating of the positive tone AZ9260 photoresist. Spin coating and lithography parameters were optimized to achieve smooth and vertical sidewalls. Copper interconnects having an aspect ratio up to 6 and a pitch size of 25 µm were electroplated in the fabricated resist mold. Due to a very small pitch size, the total number of interconnects per cm2 chip area is 160 000, which is much larger than the conventional solder-based interconnects. The electrical resistance of the electroplated copper interconnects was measured by 4-probe kelvin measurement configuration and was found to be in the range of 8–10 mΩ and the corresponding electrical resistivity was calculated as 2.4 µΩ cm. Such low resistive interconnects can carry much larger electrical current without significant electrical loss, which is ideally suitable for next generation packaging applications. X-ray diffraction has shown the presence of the (2 2 0) texture along the length of electroplated copper pillars. Transmission electron microscope reveals the presence of nanoscale copper twins along the length of copper interconnects.

Structure and migration of (112) step on (111) twin boundaries in nanocrystalline copper

Pulse-electroplated copper that contains a high density of {111}/⟨112⟩ nanotwins has been found to greatly improve the yield strength while maintaining good electrical conductivity. The thermal stability of nanotwins is a concern and has been studied by in situ transmission electron microscopy (TEM) characterization from 200 to 350 °C in the present work. It was found that the (112¯) twin boundary in a junction of (111)/(112¯)/(111) twins migrates to eliminate the (111) twin boundaries. We propose that it is the dominant mechanism that reduces the twin density in the range of temperature studied. The driving force is provided by the elimination of the two (111) boundaries. The inverse migration of the (112¯) twin boundary driven by a high strain is possible if enough stress has been applied to the copper, e.g., the strain introduced during pulsed electroplating. On the other hand, the migration of (111) twin boundary in the direction normal to the twin plane was not found. However, we propose that it can ...

Fabrication of High Aspect Ratio 35 μm Pitch Through-Wafer Copper Interconnects by Electroplating for 3-D Wafer Stacking

We report the fabrication of high aspect ratio (-15) ultradense (∼80000/cm 2 ) through-wafer copper interconnects by a special aspect ratio dependent electroplating technique. In this approach, electroplating process parameters were continuously varied along with varying unfilled via depth, to maintain the uniform current distribution and thus uniform metal deposition. Copper interconnects, with diameters as small as 12 μm and a pitch of 35 μm, were electroplated without any voids. Due to ultrafine pitch and extremely high number of I/Os per cm 2 , these interconnects were found to have significant potential in three-dimensional (3-D) wafer stacking and other high-density electronic packaging applications.

Effect of SF6 flow rate on the etched surface profile and bottom grass formation in deep reactive ion etching process

While deep reactive ion etching (DRIE) has proven to be a boon for silicon micromachining applications, certain factors still exist which affect the satisfactory performance of DRIE. Some of the process limitations include bottom grass formation, RIE lag, loading and notching effects and aspect ratio dependent etching. This paper presents the effect of SF6 flow rate and etching/passivation cycle time on the etched shape profile and bottom grass formation. Rectangular trenches of varying widths are etched using Alcatel etching system. Critical DRIE process parameters, such as SF6 flow rate and ratio of etching and passivation cycle time, are varied to explore the dependence of etched shape profile on these parameters. It is found that low SF6 flow rate, i.e. 250 sccm, results in relatively smooth bottom surface. As SF6 flow rate is increased, bottom surface roughness increases and grass forms on the bottom of etched trenches. Shape of etched surface profile was found to be changed from positive profile to negative profile, when the SF6 flow rate was increased. Ratio of etching/passivation cycle was also found to be critical for prevention of bottom grass formation. DRIE process parameters were optimised to get smooth and vertical sidewalls.

High Aspect Ratio Vertical Through-Vias for 3D MEMS Packaging Applications by Optimized Three-Step Deep RIE

This paper reports the etching of high aspect ratio (>30), vertical through-vias having an opening dimension as small as 10 μm, by a simple, three-step deep reactive ion etching (RIE) technique. Effects of individual etching parameter on the etching profile were demonstrated and then these parameters were optimized to achieve vertical and smooth sidewalls. Effect of platen power on controlling the perpendicularity of through-vias was found to be more dominant than other etching parameters. These optimized etching parameters were used to create through-vias; however, it was found that the etching profile remained vertical up to a certain depth and started tapering after that. To maintain this vertical etching profile at higher etch rate, higher plasma energy was required, which was provided by increasing the platen power in three steps. Three different platen powers (i.e., 12, 14, and 16 W) were used for different etching durations. A 200 nm aluminum layer was used as an antinotching layer to prevent the lateral etching of vias at the bonding interface and enhanced the vertical etched profile even in the case of over etching. The scanning electron microscope showed that the etching profile was completely vertical even at an etching depth as large as 510 μm. High aspect ratio interconnects were fabricated by the void-free copper electrodeposition, which will be utilized in the three-dimensional (3D) microelectromechnical systems (MEMS) packaging applications.

Fabrication of high aspect ratio 35 /spl mu/m pitch interconnects for next generation 3-D wafer level packaging by through-wafer copper electroplating

3-D wafer level packaging is one of the key technologies to fabricate next generation compact, highly dense and high speed electronic devices. In order to realize these future nanoscale IC devices, fabrication of through-wafer interconnects with ultra fine pitch, is the foremost requirement. High aspect ratio through-wafer interconnects connect several devices in vertical axis and thus offer the shortest possible interconnection length. Due to the shortest interconnect length, parasitic losses and time delay during signal propagation is the minimum, which result in faster speed. In this paper, we report the fabrication of very high aspect ratio (~15) ultra fine pitch (-35 mum) through-wafer copper interconnects by innovative electroplating process. In this technique, process parameters are continuously varied as the electroplating process goes on. To reduce the chances of void formation and to ensure the complete wetting of via surface with copper electrolyte, hydrophilic nature of vias surface is increased. Copper interconnects having diameter as low as 15 mum and height as high as 400 mum have been fabricated by above technique. Vertically standing and smooth copper interconnects with very fine grains are obtained, which are characterized by SEM