Pradyumn Chaturvedi

Carrier-Based Neutral Point Potential Regulator With Reduced Switching Losses for Three-Level Diode-Clamped Inverter

This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles.

Switching Losses and Harmonic Investigations in Multilevel Inverters

Abstract Use of conventional two-level pulse width modulation (PWM) inverters provide less distorted current and voltage but at the cost of higher switching losses due to high switching frequencies. Multilevel inverters are emerging as a viable alternative for high power, medium voltage applications. This paper compares total harmonic distortion and switching losses in conventional two-level inverters with multilevel inverters (three-level and five-level) at different switching frequencies. An optimized switching frequency has been obtained for a lower level of total harmonic distortion and switching losses. Diode-clamped, three-phase topology is considered for study. A sinusoidal PWM technique is used to control the switches of the inverter. Simulation study confirms the reduction in harmonic distortion and switching losses as the number of the levels increases.

Multi-pulse converters as a viable solution for power quality improvement

Power quality is the major area of research interest amongst scientists. This is because of awareness created by IEEE 519-1992 like standards which implies the utility as well as consumers of electric power to improve the power quality. This paper investigates the potential of multi-pulse converter to be used as power quality solution. Six, twelve, eighteen and twenty four pulse converters have been modeled and simulated in Matlab environment. A vast comparison is also presented among them

Carrier Based Common Mode Voltage Reduction Techniques in Neutral Point Clamped Inverter Based AC-DC-AC Drive System

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine’s bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.

Investigations on Different Multilevel Inverter Control Techniques by Simulation

This paper presents simulation studies on different control techniques of 3- and 5- level diode clamped multilevel inverters i.e. sinusoidal PWM, selective harmonic elimination, and optimized harmonic PWM techniques. Paper contributes towards the detailed simulation and analysis of these techniques which has not been given in previous work. The performance of each technique has been investigated based upon reduction in total harmonic distortion. For simulation, Matlab/Power System Blockset/PowerGUI has been used.

Carrier-Based Common Mode Voltage Control Techniques in Three-Level Diode-Clamped Inverter

Switching converters are used in electric drive applications to produce variable voltage, variable frequency supply which generates harmful large dv/dt and high-frequency common mode voltages (CMV). Multilevel inverters generate lower CMV as compared to conventional two-level inverters. This paper presents simple carrier-based technique to control the common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD) by adding common mode voltage offset signal to actual reference voltage signal. This paper also presented the method to optimize the magnitude of this offset signal to reduce CMV and total harmonic distortion in inverter output voltage. The presented techniques give comparable performance as obtained in complex space vector-based control strategy, in terms of number of commutations, magnitude, and rate of change of CMV and harmonic profile of inverter output voltage. Simulation and experimental results presented confirm the effectiveness of the proposed techniques to control the common mode voltages.

Piezoelectric energy harvester design and power conditioning

Energy harvesting is fascinating area of research now when the whole world is looking for green energy as an alternative source. This paper describes the design of energy harvester prototype and the power conditioning circuit. The optimization of extracted power out of the piezoelectric tile has been presented. The generation of electric energy when some load is applied on the sensors either in the form of direct strain or ambient vibration depends upon various factors such as number of piezoelectric transducers, electromechanical coupling coefficient of the piezoelectric sensors, amount of load applied, and also on the scheme of arrangement. Energy harvester floor tile has been designed with very inferior quality piezoelectric diaphragms which are used in buzzers. An efficient way has been presented to capture the generated energy via dedicated IC and boost it by a converter to get regulated output for charging the batteries of smart phones. The complete charge cycle has been studied for the developed system. The simulation and experimental studies have been successfully carried out. The model design and testing was purely for studying the energy generation and capturing phenomenon in an efficient manner. It can be implemented to generate large power by suitably considering the several factors mentioned above and implementing it on the large scale.

A simple carrier-based neutral point potential regulator for three-level diode clamped inverter

Three-level diode clamped inverter is a proven technology nowadays in medium and high power applications. Despite of its several advantages such as harmonic reduction and achieving high voltage and high power capabilities without series and parallel connections of switching devices, neutral point potential (NPP) variation is the inherent problem with this topology. This paper presents a simple NPP regulator based on addition of offset voltage to the reference sinusoidal voltages. This not only regulates the NPP, but also reduces the output voltage and current harmonics of the inverter. Simultaneously, second harmonic get reduced which may otherwise produce torque pulsations, harmonic currents and power losses. Simulation and experimental results have been presented to validate the concept.

Harmonics and common mode voltage reduction in multilevel SPWM technique

Conventional 2-level PWM inverters generate high dv/dt and high frequency common mode voltages which is very harmful in electric drives applications. It may damage motor bearings, conducted electromagnetic interferences, and malfunctioning of electronic equipments. This paper presents the simple methods to control the harmonics as well as common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD), and common mode voltage off-set voltage addition method. Simulation results obtained in Matlab/Power System Blockset toolbox confirms the effectiveness of these simple methods to control common mode voltages. Experimental results presented have been obtained using dSpace 1104.

Modeling, simulation and analysis of three-level neutral point clamped inverter using Matlab/Simulink/power system blockset

Current and voltage harmonics have attracted growing interest with the increase in use of static power converters. These converters produce distorted current and voltage waveforms. The result is harmonic pollution that degrades the power quality. To provide safe operation and to meet harmonic standards such as IEEE 519, it is necessary to eliminate harmonic distortion and improve power quality of the system. This paper presents detailed modeling, simulation and analysis of neutral point clamped three-level inverter. Various performance parameters of multilevel inverters have been investigated with three-phase induction motor load. Besides maintaining DC bus voltage balance, a significant reduction is seen in voltage distortion at neutral point in the simulation. The viability of using three-level neutral point clamped inverter in high power systems is proven by simulation using Matlab/Simulink/power system blockset. The space vector modulation (SVM) technique has been employed to get rid of common mode voltages by switching among different states in SVM