Prakash Krishnamoorthy

Quotient prediction for low power division

This work presents a variation of the non restoring division algorithm that has been optimized for low power consumption. The approach uses the value of the partial remainder at any stage in the computation to predict the quotient bits for a certain number of steps thereby allowing an equal number of computation steps to be skipped. This results in a significant reduction in switching activity in the computational stages. Simulations using the novel divider show up to 40% reduction in sequential switching activity and 20% reduction in combinational switching activity. On an average, this method uses 59% less addition operations as compared to the regular non restoring division algorithm.

On-chip Clock Testing and Frequency Measurement

This work presents a method to measure the frequency of an on-chip test clock in relation to a reference clock. Frequency measurement is accomplished by counting pulses of both test and reference clocks, albeit adjusting the reference clock pulse count to estimate the number of pulses that the test clock is expected to see. The proposed method places no constraints on the frequency relationship between the test and reference clocks which allows the reference clock frequency to be any multiple δ (1 <; δ ≤ 1) of the test clock frequency. Doing so allows a high degree of flexibility and a wide range of scenarios for which this approach could be deployed to measure the frequency of an unknown clock. Applications of this approach range from calibrating the frequency of on chip at speed test clocks for DFT, measurement of ppm of clocks subject to variations in process, temperature, spread spectrum effects among other considerations. The method also guarantees cycle to cycle accuracy in frequency measurement. Multiple on chips clocks can be tested using one instance of this method when the frequency information of all clocks to be tested is made available in specific register files.

Power aware transformation of bandlimited signals

This work presents an universal, lossless, linear, low complexity data transformation algorithm based on the sampling theorem that significantly reduces the complexity of operations in data processing systems. While many lossy and lossless compression methods are in existence, the data compressed by such methods cannot be directly processed by signal processing systems without decompression due to the non linear nature of most data compression algorithms. If there were linear compression method in existence, then compressed data could directly be passed to digital signal processing systems. Doing so significantly reduces the complexity of signal processing operations including additional benefits in the form of reduced power dissipation, improved signal integrity and better bandwidth utilization. This approach can be used in applications for the storage and retrieval of data from storage mediums such as read channels, system and processor interconnects including memory buses. System level simulations show that this method not only reduces the amount of data, but also improves performance due to improved signal integrity and significant reduction in power dissipation (upto 15% reduction) associated with the processing of multimedia content.