Pranay Chaudhuri

Parallel algorithms for analyzing activity networks

Parallel algorithms for analyzing activity networks are proposed which include feasibility test, topological ordering of the events, and computing the earliest and latest start times for all activities and hence identification of the critical activities of the activity network. The first two algorithms haveO(logn) time complexity and the remaining one achievesO(logd log logn) time bound, whered is the diameter of the digraph representing the activity network withn nodes. All these algorithms work on a CRCW PRAM and requireO(n3) processors.

Fast parallel graph searching with applications

This paper presents fast parallel algorithms for the following graph theoretic problems: breadth-depth search of directed acyclic graphs; minimum-depth search of graphs; finding the minimum-weighted paths between all node-pairs of a weighted graph and the critical activities of an activity-on-edge network. The first algorithm hasO(logdlogn) time complexity withO(n3) processors and the remaining algorithms achieveO(logd loglogn) time bound withO(n2[n/loglogn]) processors, whered is the diameter of the graph or the directed acyclic graph (which also represents an activity-on-edge network) withn nodes. These algorithms work on an unbounded shared memory model of the single instruction stream, multiple data stream computer that allows both read and write conflicts.

An 0(log n) parallel algorithm for strong connectivity augmentation problem

A synchronised parallel algorithm for the strong connectivity augmentation problem is presented. Its depth is 0(log n) using 0(n 3) processors on a concurrent read, concurrent write parallel random access machine.

Distributed algorithm for analysing activity networks

An algorithm for computing early start time, late start time and slack time, for each activity of an activity network on a distributed computation model, is proposed. Computational complexity and proof of correctness of the distributed algorithm are also given.

A self-stabilizing graph algorithm: Finding the cutting center of a tree

The cutting number of a node i in a connected graph G is the number of pairs of nodes in different components of G − {i}. The cutting center consists of the set of nodes of G with maximal cutting number. This article presents a self-stabilizing algorithm for finding the cutting numbers for all nodes of a tree T = (V T, E T) and hence the cutting center of T. It is shown that the proposed self-stabilizing algorithm requires O(n 2) moves. The algorithm complexity can also be expressed as O(n) rounds. †E-mail: hthompson@uwichill.edu.bb

Efficient algorithms for some graph problems on a tree-structured parallel computer

In this paper, we present efficient parallel algorithms for breadth-first and depth-first search of graphs, finding the transitive closure of a directed graph, topological sorting of the nodes of a directed acyclic graph, and all-pairs youngest common ancestors of a directed tree on a tree-structured computer. Assuming that all the graphs and trees under investigation consist of n nodes, these algorithms achieve 0(n log n) time bound except for all-pairs youngest common ancestors problem which requires 0(n 2 log n) time—all with 0(n) processors. In all cases the costs (i.e. (parallel running time × number of processors) products) of our algorithms are better than those of the previously known parallel algorithms, except the last one where the cost is identical to that of the corresponding best known parallel algorithm.

An adaptive parallel algorithm for analyzing activity networks

A parallel algorithm for analyzing activity networks is presented. The model of computation is a shared memory single-instruction-stream, multiple-data-stream computer that does not allow read or write conflicts. The algorithm is adaptive in the sense that it takes O(n^1^+^h) time with n^1^-^h processors for an activity network with n events (nodes), where h (0=

Scheduler for realtime process control

Abstract Microcomputers are increasingly being used in various process control systems. A recent trend is to use them in multiprogrammed realtime environments rather than as dedicated controllers. The paper describes the design of a scheduler for realtime process control using microcomputers. For simplicity, a static-priority-based round-robin scheduling policy is used whereby the working time slice can be varied for the different processes. The memory size for the process scheduler is estimated at approximately 1 kbyte using the Intel 8085 instruction set.