Priyalal Kulasinghe

Embedding binary trees into crossed cubes

The recently introduced interconnection network, crossed cube, has attracted much attention in the parallel processing area due to its many attractive features. Like the ordinary hypercube, the n-dimensional crossed cube is a regular graph with 2/sup n/ vertices and n2/sup n-1/ edges. The diameter of the crossed cube is approximately half that of the ordinary hypercube. These advantages of the crossed cube motivated the study of how well it can simulate other networks such as the complete binary tree. We show that the (2/sup n/-1) node complete binary tree can be embedded into the n-dimensional crossed cube with dilation 1. >

Connectivity of the crossed cube

It was speculated that the connectivity of the n-dimensional crossed cube is n. In this paper we prove that the result is true.

Optimal realization of sets of interconnection functions on synchronous multiple bus systems

We develop a formal and systematic methodology for designing an optimal multiple bus system (MBS) realizing a set of interconnection functions whose graphical representation (denoted as IFG) is symmetric. The problem of constructing an optimal MBS for a given IFG is NP-hard. In this paper, we show that polynomial time solutions exist when the IFG is vertex symmetric. This is the case of interest for the vast majority of important interconnection function sets. We present a particular partition (which can be found in polynomial time) on the edge set of a vertex symmetric IFG, that produces a symmetric MBS with minimum number of buses as well as minimum number of interfaces. We demonstrate several advantages of such an MBS over a direct-link architecture realizing the same IFG, in terms of the number of ports per processor, number of neighbors per processors, and the diameter.

Algorithmic mapping of feedforward neural networks onto multiple bus systems

This paper addresses the problem of mapping a feedforward ANN onto a multiple bus system, MBS, with p processors and b buses so as to minimize the total execution time. We present an algorithm which assigns the nodes of a given computational layer (c-layer) to processors such that the computation lower bound [N/sup l//p]t/sub p//sup l/ and the communication lower bound [N/sup l//b]t/sub c/ are achieved simultaneously, where N/sup l/ is the number of nodes in the mapped c-layer l and t/sub p//sup l/ and t/sub c/ are the computation and communication times, respectively, associated with a node in the layer. When computation and communication are not overlapped, we show that the optimal number of processors needed is either 1 or p, depending on the ratio t/sub p//sup l//t/sub c/. When computation and communication are overlapped, we show that the optimal number of processors needed is either 1 or ([t/sub p//sup l//t/sub c/])b. We show that there is a unique arrangement of interfaces such that the total number of interfaces is minimum and the optimal time is reached. Finally, we compare the relative merits of the MBS simulating ANNs over the recently introduced checkerboarding scheme.

On the complexity of optimal bused interconnections

This paper addresses the combinatorial problem of constructing a minimal cost, bused, interconnection among a set of modules (or processors). Although some work has been reported on bused interconnection between modules, the compuational complexity of the problem has not been previously addressed. We show that the optimization problem of finding a minimal cost interconnection among modules to realize a certain set of data transfers is NP-Hard. >

On the multiply-twisted hypercube

In this paper, we prove that the multiply-twisted hypercube is a Cayley graph and hence it possesses the desirable properties such as vertex symmetry, optimal fault tolerance, and small node degree. We also prove the conjecture that the 2n−1 node complete binary tree is a subgraph of the 2n node multiply twisted hypercube.

On the complexity of designing optimal branch-and-combine clock networks

Recently, an unconventional clock distribution scheme, called Branch-and-Combine (BaC) was proposed. The scheme is the first to guarantee constant skew upper bound irrespective of the clocked networks size. In BaC clocking, a set of interconnected nodes perform simple processing on clock signals such that the path from the source to any node is automatically and adaptively selected such that it is the shortest delay path. The graph underlying a BaC network is constrained by the requirement that each pair of adjacent nodes is in a cycle of length /spl les/k, where k is the feature cycle length. The graph representing such a network is called a BaC(k) graph. The feature cycle length (k) is an important parameter upon which skew bound and node function depend. We study the complexity of the general problem of designing a minimum cost BaC network for clocking a data processing network of arbitrary topology so that a certain feature cycle length is satisfied. We define two versions of the problem, differing in the way we are allowed to place edges in the graph representing the BaC network. We show that, in both cases, the general optimization problem is NP hard. We also provide efficient heuristic algorithms for both versions of the optimization problem. When k=2, the two versions of the optimization problem become the same and can be solved in polynomial time. For k=3, the complexity is still unknown.

A general scheme for constructing optimal bus based architectures for hypercubes

We present a general methodology for constructing optimal bus based hypercubes. The methodology encompasses previously proposed bus based hypercubes. If mn is the total number of different unidirectional Multiple Bus Systems (MBSs) that can optimally emulate the n‐dimensional hypercube, then σn≤ mn≤σn, where σn denotes the number of unlabeled trees on n edges. Each such MBS is symmetric with respect to the buses and processors, and has n + 1 ports per processor, whereas the hypercube has 2n ports per processor. We choose one specific MBS from those optimal MBSs and demonstrate its other attractive properties. It can simultaneously perform data transfers across as many as n dimensions. It is fault tolerant with respect to a bus, a processor, or an interface failure. We also show how to construct optimal bidirectional MBSs emulating hypercubes. The new architecture is very similar to the unidirectional one; yet it has half the number of buses and half the number of interfaces. It can simultaneously transfer data across as many as n dimensions. Its fault tolerance is similar to that of the unidirectional MBS.

An optimal algorithm for layered wheel floorplan designs

In this paper, we present an efficient algorithm to solve the orientation optimization problem for a layered wheel floorplan. The strategy used is to generate all the nonredundant implementations for the floorplan. The computational complexities of the algorithm depend on the actual dimensions of the cells in the floorplan. In the best case, it takes O(n 2 ) time and O(n) space, where n is the number of layers in the floorplan. In the worst case, it takes O(2 n ) time and O(2 n ) space. Furthermore, we prove that the time and space complexities for the worst case are optimal. A set of conditions is obtained to check whether the floorplan belongs to the worst case. Using these conditions, we show that even though the worst case is theoretically unavoidable it is not encountered in practical situations where the cell dimensions are bounded.

On Achieving Maximum Performance in Time-Varying Arrays

Several important computationally intensive algorithms can be implemented on special purpose VLSI arrays. A number of such algorithms naturally map onto either heterogenous arrays or arrays employing PEs with switchable functions, or both. In many cases, such designs are the only known ones for VLSI implementation. Synchronization is generally achieved by assuming that the time required to perform basic PE computations is uniform, although the PEs perform different functions and may change their functions at different algorithmic steps. This simplistic approach may result in significant performance degradation. This paper addresses the properties, performance, and theory of time-varying heterogeneous arrays for the objective of achieving maximum performance. A systematic method for collision avoidance is formally introduced and analyzed. Our approach is based on dynamically balancing a two-level pipelined array through the use of a set of buffers. Another set of buffers is used to guarantee data synchronization. We show that if the initial delays (PE execution times) and the time variances are deterministic, an equivalent time-invariant array can be constructed (in polynomial time) which is optimal in speed. We describe a method for estimating the upper bound on computational time when array time variance is nondeterministic. Our method requires only knowledge of the bounds on initial delays.