Promod Kumar

FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems

Framework is developed for estimation of power at pre register transfer level (RTL) stage for structured memory sub-systems. Power estimation model is proposed specifically targeting power consumed by clock network and interconnect. The model is validated with VCD-based simulation on back-annotated netlist of an 8 MB memory sub-system used as video RAM (VRAM) for high-end graphics applications. This methodology also forms the basis for low-power exploration driving floor plan choice, gating structure of data, and clock network. We demonstrate 57% reduction in dynamic power by using low-power techniques for the 8 MB VRAM used as frame buffer in a graphics processor. FALPEM can be extended to other applications like processor cache and ASIC designs.

Built in self test for low cost testing of a 60MHz synchronous flash memory

Describes the application of a methodology of testing, based on an embedded built in self test (BIST) circuitry. Applying the described methodology to a standard flash memory with 60MHz burst read operation option, it is possible to obtain a maximum test coverage at package level, using a low cost automatic test equipment (ATE), with a speed of 20MHz only, commonly used for asynchronous flash memories. In addition, it is possible to extend the use of the BIST during the electrical wafer sort (EWS) test step. This makes possible speed classification at this level and helps to reduce the test time of each read operation, using 5mHz ATE.

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs

Dual Rail SRAMs are widely used to enable Dynamic Voltage and Frequency Scaling (DVFS) in SRAMs where array voltage cannot be scaled down. DVFS operating points are limited by maximum differential supported between two supplies of the SRAM. To extend gains of DVFS, we propose a Low Standby Power - Capacitively Coupled Sense Amplifier (LSTP-C2SA) that enables further lowering of periphery supply in Dual Rail SRAMs without leading to SRAM cell instability. We present a design method to optimally size the coupling capacitance in LSTP-C2SAs. Designs with LSTP-C2SA are shown to consume 43% lesser read power in DVFS operation at 0.4V in 28nm UTBB FD-SOI when compared to an implementation with standard latch sense amplifier. Silicon measurements confirm LSTP-C2SA functionality at 0.35V.

A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35–1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables bit-interleaving. The proposed assist scheme can be combined with conventional assist schemes to further lower minimum write operational voltage of the SRAM by 70–130 mV at iso-performance without causing reliability concerns. A 32 kb instance is fabricated in 28-nm UTBB-FDSOI technology and efficiency of the proposed scheme is demonstrated with lowest write voltage of 0.32 V. Multiple read assist schemes have been used to simultaneously lower read voltage to 0.35 V. 50 MHz operation is measured when integrated in a DSP processor at 0.358 V. Low voltage and wide voltage range figure of merits are also defined to benchmark the proposed solutions with other works.