Prosenjit Mal

The circuit designs of an SRAM based look-up table for high performance FPGA architecture

Look-up table (LUT) circuits are the core component of all Field Programmable Gate Arrays (FPGAs) architectures. Although considerable research has been done regarding the high-level architecture of different LUTs, very little has been done on the circuit-level description of the LUT. Though traditional LUT designs use NMOS transistors to implement pass-gates that save area and increase speed, large LUT designs require several pass gates in series. Unfortunately, multiple pass transistors in series will degrade the logic high level and thus jeopardize signal integrity. This paper explores different circuit-level implementations of the LUT circuitry with consideration towards the relative design trade-offs.

Design and demonstration of a configurable architecture for smart pixel research

The design, demonstration and evaluation of a general purpose, smart pixel based photonic information processing system is presented. Based on a photonic VLSI device technology implemented in 1.5 /spl mu/m CMOS, each pixel incorporates a photoreceiver with a RISC processor and produces a device that is suitable for prototyping photonic information processing systems.

Design and demonstration of an optical field programmable gate array

The design, demonstration and evaluation of a general purpose, field programmable smart pixel based photonic information processing system is presented. This novel architecture incorporates photoreceiver cells into a field programmable gate array (FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We report here on the photoreceiver design methodology and measure device performance.

Characterization and performance evaluation of CMOS photodetectors implemented in optoelectronic circuits

The ability to produce a high performance monolithic CMOS photodetector could enable greater use of optics in short-distance communication systems and photonic information processing systems. The quest for a photodetector compatible with a high-volume high-yield CMOS process has yet to produce a clear winner, and has proven quite challenging. We present in this paper several different photodetector structures implemented with a conventional CMOS fabrication process that can be incorporated into optical data links and information processing systems. As a result, it combines the parallelism associated with optics and the data processing capabilities associated with CMOS logic.

Development of a general purpose configurable architecture for smart-pixel research

The ever-increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics devices and conventional data processing circuitry. Based on the smart-pixel architectures first developed in the last decade, the architecture presented here monolithically integrates optical sensors with silicon CMOS-based circuitry to produce a generically programmable smart-pixel array. Two generations of the architecture are described and compared. We have proposed a reconfigurable photonic information-processing chip based on photonic VLSI device technology. Integrating detectors into a SIMD array removes the bottleneck associated with fetching slices of data. By fabricating the detectors along with logic circuits in a bulk CMOS process, the cost is minimized. The modular nature of the array organization facilitates replication of the configurable architecture for smart-pixel research (CASPR) concept into large arrays without a significant increase in design overhead. Thus, the CASPR architecture can provide the maximum flexibility associated with a reconfigurable smart-pixel array. Finally, we implement two design iterations of the CASPR architecture and show how the architecture might be used in a page-oriented optical data processing application.

Programmable photoreceiver module for incorporation in an optical field-programmable gate array

The design, demonstration and evaluation of a general purpose, field programmable smart pixel based photonic information processing system is presented. This novel architecture incorporates programmable photoreceiver cells into a field programmable gate array (FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We report here on the programmable photoreceiver design methodology and measure device performance.

Development of a multitechnology field-programmable gate array suitable for photonic information processing

The architecture of a novel, multitechnology field-programmable gate array (FPGA) is introduced. Based on conventional complementary metal-oxide semiconductor VLSI technology this architecture has demonstrated the feasibility of reconfigurable and programmable hardware for prototyping photonic information processing systems. We report that this new FPGA architecture will enable the design of reconfigurable systems that incorporated technologies outside the traditional electronic domain. The smart photoreceivers monolithically integrated in the new FPGA architecture can receive optically encoded signals in parallel and process them with user programmable logic hardware.

Development of a programmable photoreceiver module integrated in a multitechnology field-programmable gate array

We present her a user programmable photoreceiver block that is monolithically integrated in a new generation of multi-technology field programmable gate array (MT-FPGA). Implemented with a photonic VLSI technology the device is suitable for prototyping photonic information processing systems. We also report here on the photoreceiver design methodology in a mixed signal environment and simulation results indicating the device performance.

Development of a configurable architecture for smart pixel research (CASPR)

The design, demonstration and evaluation of a general purpose, smart pixel based photonic information processing unit is presented. Based on a photonic VLSI device technology that can be implemented using a standard 1.5-micrometers CMOS, each pixel incorporates a photoreceiver with a RISC processor and produces a device that is suitable for prototyping photonic information processing systems.

Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA’s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.