Purnawarman Musa

Design and implementation of non-linear image processing functions for CMOS image sensor

Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 64×64 pixels image sensor built in a standard CMOS Technology 0.35 μm including non-linear image processing. The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 2×2 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 40×40 mu m. The total area of the 64×64 pixels is 12.5mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (10K frames per second), minima/maxima calculations in less then one ms.

Neuro-inspired smart image sensor: analog Hmax implementation

Neuro-Inspired Vision approach, based on models from biology, allows to reduce the computational complexity. One of these models - The Hmax model - shows that the recognition of an object in the visual cortex mobilizes V1, V2 and V4 areas. From the computational point of view, V1 corresponds to the area of the directional filters (for example Sobel filters, Gabor filters or wavelet filters). This information is then processed in the area V2 in order to obtain local maxima. This new information is then sent to an artificial neural network. This neural processing module corresponds to area V4 of the visual cortex and is intended to categorize objects present in the scene. In order to realize autonomous vision systems (consumption of a few milliwatts) with such treatments inside, we studied and realized in 0.35μm CMOS technology prototypes of two image sensors in order to achieve the V1 and V2 processing of Hmax model.

An Implementation of Direction Cosine Matrix in rocket payload dynamics attitude monitoring

Rocket, one of the aerospace vehicle capable to being used for implement various interests in many fields, can maintain the sovereignty of the State. Rocket generally do not stand alone, but embedded with payload that contains sensors, processor, and transceiver. The payload will be equipped with Inertial Measurement Units (IMUs) which generally consists of a gyroscope and an accelerometer. This is intended to determine the rocket dynamics attitude that play an important role in the rocket control system. Problems arise considering the accelerometer and gyroscope each has its deficiencies. Accelerometer is sensitive to small external force and gyroscope has a tendency to drift. Both are not able to determine rockets heading orientation relative to Earth, thus they will require a magnetometer to solve the problem. The whole series of these deficiencies can be eliminated by combining measurement data from the three. IMU with 9 DOF and Direction Cosine Matrix algorithm are expected to produce rockets dynamics attitude data trustworthy.

Design and Implemention of ADC Implanted in 10 000Frame/s High-Speed CMOS Sensor

This paper describes the design of pipeline ADC embedded in a high speed CMOS sensor that has been designed and fabricated by Paindavoine. The idea of ADC to be embedded in the high speed cmos sensor in order to reduce power, integrated so that the output of the CMOS sensor is already in digital form. An ADC is designed using Pipeline topology with considerations is simple in the design because it just makes a stage and the next stage is duplicated, relatively high speed and have good resolution. Pipeline ADC designed using 0.35 μm CMOS technology. Pipeline ADC successfully implemented in a electronics circuit and layout. It has been fabricated. The results of simulations show that the design of pipeline ADC is working properly and can be used to handle a high speed CMOS sensor that has speed of 10 000 frames/s.