Qamrul Hasan

HW/SW architecture for speech recognition acceleration

This paper describes a new hardware architecture for fast Acoustic Model scoring in embedded speech recognition systems by integrating an 8-way data-path with a NOR Flash array. This architecture localizes computation of critical algorithms and reduces decode latency and CPU load by 50% for large acoustic models, resulting in lower word error rates for natural language speech recognition.

Streamlining HW-SW architecture development, verification and validation

The lack of code reuse in state-of-the-art verification methodologies results in long verification cycles. In this paper we present a new approach that structures the design/verification environment into 3 elements to ensure 100% reuse of verification codes across design phases: design abstraction, the abstraction-independent driver, and software applications on top of the driver. Through a real-world design project, we confirm an expected ~35% saving in verification time over the classic methodology.