Qing-Tai Zhao

Efficient field emission from ZnO nanoneedle arrays

Well-aligned arrays of ZnO nanoneedles were fabricated using a simple vapor phase growth. The diameters of the nanoneedle tips are as small as several nanometers, which is highly in favor of the field emission. Field-emission measurements using the nanoneedle arrays as cathode showed emission current density as high as 2.4 mA/cm2 under the field of 7 V/μm, and a very low turn-on field of 2.4 V/μm. Such a high emission current density is attributed to the high aspect ratio of the nanoneedles. The high emission current density, high stability, and low turn-on field make the ZnO nanoneedle arrays one of the promising candidates for field-emission displays.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

Green-light-emitting ZnSe nanowires fabricated via vapor phase growth

Stoichiometric ZnSe nanowires have been synthesized through a vapor phase reaction of zinc and selenium powder on the (100) silicon substrate coated with a gold film of 2 nm in thickness. The microstructures and the chemical compositions of the as-grown nanowires have been investigated by means of electron microscopy, the energy dispersive spectroscopy, and Raman spectroscopy. The results reveal that the as-grown materials consist of ZnSe nanowires with diameters ranging from 5 to 50 nm. Photoluminescence of the sample demonstrates a strong green emission from room temperature down to 10 K. This is attributed to the recombination of electrons from conduction band to the medium deep Au acceptors.

Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs

The effect of dopant segregation (DS) on the electrical behavior of silicon-on-insulator Schottky barrier MOSFETs (SB-MOSFETs) is investigated. Ion implantation with arsenic and boron and subsequent silicidation is used to create highly n- and p-doped interface layers at the silicide-silicon interface. As a result, a strong band bending occurs at the silicide-silicon interface giving rise to a lowering of the effective Schottky barrier height. In turn, an increased electron as well as hole injection into the channel leads to improvements of the off- and on-state of the SB-MOSFETs. Using dopant segregation n-type as well as p-type SB-MOSFETs with nickel silicide source/drain electrodes have been fabricated exhibiting an inverse sub-threshold slope close to the thermal limit and showing one order of magnitude higher on-currents if compared to SB-MOSFETs without DS. In essence, the use of dopant segregation allows the fabrication of high performance Schottky barrier MOSFETs.

Effective Schottky barrier lowering in silicon-on-insulator Schottky-barrier metal-oxide-semiconductor field-effect transistors using dopant segregation

We present an investigation of the use of dopant segregation in Schottky-barrier metal-oxide-semiconductor field-effect transistors on silicon-on-insulator. Experimental results on devices with fully nickel silicided source and drain contacts show that arsenic segregation during silicidation leads to strongly improved device characteristics due to a strong conduction/valence band bending at the contact interface induced by a very thin, highly doped silicon layer formed during the silicidation. With simulations, we study the effect of varying silicon-on-insulator and gate oxide thicknesses on the performance of Schottky-barrier devices with dopant segregation. It is shown that due to the improved electrostatic gate control, a combination of both ultrathin silicon bodies and gate oxides with dopant segregation yields even further improved device characteristics greatly relaxing the need for low Schottky barrier materials in order to realize high-performance Schottky-barrier transistors.

Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

We present gate all around strained Si (sSi) nanowire array TFETs with high I_ON (64μA/μm at V_DD=1.0V). Pulsed I-V measurements provide small SS and record I₆₀ of 1×10^-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and I_ON. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

An Improved Si Tunnel Field Effect Transistor With a Buried Strained

We report on experimental and simulated results of tunneling field-effect transistors (TFETs) with a Si channel and a strained Si1-xGex source. The fabricated TFET with a tensile strained Si channel shows comparably large on-currents and a subthreshold slope of 80 mV/dec at 300 K for a drain current range of three orders of magnitude. A novel TFET structure is proposed to enhance the on-currents by using a buried Si1-xGex source. The overlap between the top thin Si channel and the buried SiGe source increases the tunneling area. Simulations indicate that this structure significantly improves the performance.

\hbox{Si}_{1-x}\hbox{Ge}_{x}

Ultrathin Ni silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi2 layers were grown at temperatures > 450°C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi2 is about one order of magnitude lower than that of a NiSi layer on both As- and B-doped SOI and SSOI.

Source

A nanometer patterning method, based on local oxidation of silicide layers, was used to pattern epitaxial CoSi2 layers. A feature size as small as 50 nm was obtained for 20 nm epitaxial CoSi2 layers on Si(100) after patterning by local rapid thermal oxidation in dry oxygen. A Schottky source/drain metal–oxide–semiconductor field effect transistor with epitaxial CoSi2 on p-Si(100) was fabricated using this nanopatterning method to make the 100 nm gate. The device shows good I–V characteristics at 300 K.

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

This letter presents experimental results on tunneling field-effect transistors featuring arrays of Ω-gated uniaxially strained and unstrained silicon nanowires. The gate control of a SiO2/poly-Si gate stack is compared with a high-k/metal gate stack. Steep inverse subthreshold slopes down to 76 mV/dec and relatively high on-currents were achieved with the combination of high-k/metal gate and strained silicon nanowires. We observed negative differential conductance in the output characteristics, which we attribute to hot-carrier effects in the strong electric fields at the reverse-biased tunnel junction.