Qingyu Cui

Inkjet printed fine silver electrodes for all-solution-processed low-voltage organic thin film transistors

Inkjet printed silver (IJP Ag) source/drain (S/D) and gate electrodes were incorporated into a bottom-gate bottom-contact organic thin film transistor (OTFT) architecture to develop all-solution-processed low voltage OTFTs. With well controlled ink wetting on a cross-linked polyvinyl-alcohol surface, IJP Ag S/D electrode pairs were fabricated with controllable short channels down to 20 μm using a Dimatix 2831 inkjet printer with a 10 pL cartridge, and formed good contacts with the organic semiconductor layer. IJP gate electrodes with a low flat surface profile were also achieved to obtain OTFTs of high quality gate dielectric layer for low leakage current. The fabricated low voltage all-solution-processed OTFTs present good device performance with a low operation voltage below 2 V, a mobility of 0.3 cm2 V−1 s−1, and an ON/OFF current ratio larger than 104.

All-Solution-Processed Low-Voltage Organic Thin-Film Transistor Inverter on Plastic Substrate

In this paper, all-solution-processed low-voltage organic thin-film transistor inverters on polyethylene naphthalate plastic substrate were achieved in the bottom-gate bottom-contact device configuration. In the devices, 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene was used as the channel layer, and ultraviolet cross-linked polyvinyl alcohol was used as the gate dielectric layer. With optimized inkjet jetting process parameters and a proper polymer dielectric substrate surface, fine silver electrodes were formed as the source, drain, and gate electrodes. The maximum processing temperature was 150°C. The devices show promising performance with a mobility of 0.8 cm2/(V·s), a subthreshold swing of 100 mV/decade and an ON/OFF ratio of about 104. The fabricated diode-load inverter has a high dc voltage gain up to 67.3 at a supply voltage of 3 V.

Controlling the surface wettability of the polymer dielectric for improved resolution of inkjet-printed electrodes and patterned channel regions in low-voltage solution-processed organic thin film transistors

A facile method for realizing both inkjet printed electrodes with improved resolution and patterned semiconductor islands was developed to fabricate all solution processed low-voltage organic thin film transistors (OTFTs). By reducing the surface wettability of the polymer gate dielectric layer through coating of a self-assembled monolayer (SAM), fine and narrow inkjet printed source/drain electrodes (a line width of about 35 μm) and short channels (about 15 μm) were formed with very good yield and uniformity using an inkjet printer with a 10 pL drop volume print head and limited registration accuracy. The coated SAM layer was then selectively removed by ultraviolet ozone treatment to create patterned wettable and less wettable regions to form self-assembled organic semiconductor islands. The fabricated low voltage OTFTs present a high quality semiconductor/dielectric interface and good device performance.

Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes, and relatively high gain, the unipolar zero-VGS-load logic design is widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this paper, a simple NM model clarifying the relationship between the NM and electrical/device parameters is developed for the zero-VGS-load inverter. The model is verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory cell design is discussed.

Low Voltage Organic/Inorganic Hybrid Complementary Inverter With Low Temperature All Solution Processed Semiconductor and Dielectric Layers

A novel organic/inorganic hybrid integration architecture was developed to realize low-voltage complementary inverters with low temperature (not exceeding 150°C) solution processed semiconductor and dielectric layers. The p-type organic transistor and n-type zinc-oxide transistor used different approaches to reduce the operation voltage, and can thus be easier to be integrated with compatible solution based processes.

Annealing-Free Solution-Processed Silver Nanowire-Polymer Composite Transparent Electrodes and Flexible Device Applications

By using ultrahigh aspect ratio (>2000:1) silver nanowires (AgNWs) and ethanol-diluted poly (3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) as the overcoating layer, we achieved flexible AgNW-polymer composite transparent electrodes of high conductivity and optical transmittance using facile solution processes at room temperature without annealing. The electrodes were applied in fabricating flexible capacitive pressure sensors and organic photovoltaic (OPV) devices. The pressure sensor with the composite electrodes presents three times higher sensitivity than that using ITO electrodes. A flexible 4 × 4 sensor array was also fabricated, which well proved the capability of the electrodes for spatially electronic signal collection and transmission. The fabricated flexible OPV device has a power conversion efficiency of 1.83%, which proves the potential of the electrodes for multilayer integration in optoelectronic device applications.

Dual-

Threshold voltage (V_th) control using different metal gates (aluminum and gold) was applied to realize dual-V_th low-voltage solution processed organic thin film transistors (OTFTs). In the devices, the low-operation voltage was realized based on a channel engineering approach instead of using large gate dielectric capacitance, therefore, a relatively thick and low-dielectric constant polymer dielectric layer can be used. The devices present a mobility about 1.0 cm²/(V·s), ON/OFF ratio of 10⁵ and small subthreshold swing of 100 mV/decade with the maximum processing temperature not exceeding 100 °C. It was found that, even with a 400-nm thick polymer dielectric layer, since possible charge trapping effects was effectively suppressed by the crosslinking processes, well controlled V_th was achieved. Both unipolar single-V_th and dual-V_th inverters were fabricated, clearly showing the influence of V_th on the circuit operation and improved performance with the dual-V_th OTFT technology.

V_{\rm th}

This letter presents an analytical circuit yield model for zero-VGS-load thin-film transistor (TFT) logic circuits, which describes the circuit yield as a function of the circuit complexity, threshold voltage dispersion of TFTs, and circuit design parameters. By comparing the calculation result through the model with that by Monte Carlo statistical circuit simulations, the model is proved to be capable of providing a simple and effective way to predict the yield of a given zero-VGS-load TFT circuit design, and is thus applicable for TFT performance evaluation or device and process optimization.

Low-Voltage Solution Processed Organic Thin-Film Transistors With a Thick Polymer Dielectric Layer

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-VGS-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero-VGS-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-VGS-load logic circuits.

An Analytical Yield Model for Zero-

In this letter, ultralow-operation-voltage (<; 2 V) solution-processed organic thin-film transistors were achieved at small gate dielectric capacitance of only 12.2 nF/cm2 in the bottom-gate bottom-contact configuration. In the devices, 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene was used as the channel layer, and ultraviolet cross-linked polyvinyl alcohol was used as the gate dielectric layer. The maximum processing temperature was 100°C. The devices showed promising performance with a mobility value of about 1.0 cm2/( V·s), a subthreshold swing of about 100 mV/dec, and negligible hysteresis. The mechanism of achieving such a low operation voltage without needing large gate dielectric capacitance for the devices was discussed.