Qiuting Huang

The impact of scaling down to deep submicron on CMOS RF circuits

Recent papers reporting CMOS RF building blocks with very low current consumption have aroused much expectation in RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels for different feature sizes if robust designs are to be implemented. The need to match to 50Ω and to limit voltage gain in the input passive matching network is emphasized because it is often overlooked. At 1GHz, 0.25µm CMOS appears to be the threshold for robust, low-NF RF Front-ends with current consumption competive to todays BJT implementations.

A 0.5-mW passive telemetry IC for biomedical applications

The radiated power received by a small coil in implantable telemetry systems is less than a milliwatt. This requires a very efficient RF to DC converter, as well as the lowest possible power consumption for the biomedical sensor and data acquisition/transmisson system. This paper describes the design of a BiCMOS integrated circuit that includes a low noise amplifier, a lowpass notch filter, an A/D converter, voltage doubler/rectifier as well as a low power voltage regulator. The entire system, including the 1.7kΩ MR bridge sensor, consumes only 520µW average power @3V.

Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C/sub ox/WL if the transistors connected to its source are turned off. Such an observation, illustrated in this paper by a detailed analysis of the Yuan-Svensson D-flip-flop (D-FF) can be used to advantage both in sizing the transistors and in developing better configurations. A glitch-free, general purpose, and faster D-FF is presented here which has complementary outputs and runs at frequencies from tens of hertz to a couple of gigahertz for a 1-/spl mu/m CMOS technology. Measured maximum clock frequency of a divide-by-16 circuit is 2.65 GHz at 5 V supply, whereas that of a dual-modulus frequency prescaler, dividing by 64/65, goes up to 1.6 GHz at 5 V.

A 13.5-mW 185-Msample/s /spl Delta//spl Sigma/ modulator for UMTS/GSM dual-standard IF reception

To accommodate drastically different symbol rates, signal bandwidth and SNR requirements between WCDMA and GSM, the IF frequency, sample-rate and converter architecture are optimized for a dual-standard /spl Sigma//spl Delta/ modulator. In the system and circuit design, attention is given to low power consumption to achieve 13.5 mW at 18 MSample/s. Measured dynamic range is 53 dB for WCDMA and 84 dB for GSM.

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-/spl mu/m single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV//spl radic/Hz. The typical residual input offset is 1.5 /spl mu/V. The amplifier power consumption is 1.3 mW.

A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset

A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77/spl plusmn/0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV//spl radic/Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-/spl mu/m single-poly CMOS process.

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.

Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD

A MOSFET-only 10-bit A/D converter is described which achieves a total harmonic distortion of up to -79 dB without trimming or calibration. The maximum conversion rate is 200 ksample/s. Implemented in a 1-/spl mu/m single-poly technology, it occupies 5.12 mm/sup 2/ and consumes 12 mW from a single 5 V supply. The MOSFET-only R-2R ladder, which is the center of the successive approximation architecture, is analyzed, and design considerations, especially the device dimensions, are given. Measurements of the linear behavior of pure MOSFET ladders are presented. The offset sensitivity of the ladder is examined, and an alternative way of summing the ladder current is suggested. A fast and effective differential current comparator is described.

Uncooled low-cost thermal imager based on micromachined CMOS integrated sensor array

We present a micromachined 10/spl times/10 array of thermoelectric infrared sensors fabricated in a commercial complementary metal-oxide-semiconductor (CMOS) integrated circuit process with subsequent bulk-micromachining on wafer-scale. This array is used to demonstrate the feasibility of a low-cost thermal imager. The imager operates in ambient air, without thermal stabilization or cooling. The thermoelectric sensor principle allows one to measure dc radiation signals even without a radiation chopper. Each pixel contains an integrated heater, which allows calibration and self-testing of the imager. Addressing circuitry for the thermopiles and the heaters as well as a low-noise amplifier are integrated with the array on a single chip with a size of 5.5/spl times/6.2 mm. The imager achieves a temperature resolution of 530 mK with a low-cost polyethylene Fresnel lens. This performance allows application in presence detection, remote temperature measurement, and building control.

A 20-mA-receive, 55-mA-transmit, single-chip GSM transceiver in 0.25-/spl mu/m CMOS

This paper presents a low-power 900-MHz GSM transceiver developed in a 0.25-/spl mu/m CMOS technology. The superhet receiver, with a single intermediate frequency at 71 MHz, has an overall worst case noise figure of 8.1 dB, including all filters. The overall gain can be digitally controlled over 98-dB range. The receiver consumes only 19.5 mA from the 2.5-V voltage supply while achieving the required blocking and intermodulation performance. The direct conversion transmitter has a fully integrated phase shifter and provides a 2-mW signal to the power amplifier with a low level of spurious emissions. The transmitted Gaussian minimum shift keying signal has an RMS average phase error <2/spl deg/, and the overall current consumption of the transmitter is 55 mA.