Quang H. Trang

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Publication

Featured researches published by Quang H. Trang.

Archive | 2003

High-performance, superscalar-based computer system with out-of-order instruction execution

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Te-Li Lau; Sze-Shun Wang; Quang H. Trang

Archive | 2006

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Te-Li Lau; Sze-Shun Wang; Quang H. Trang

Archive | 1992

RISC microprocessor architecture implementing fast trap and exception state

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Quang H. Trang

Archive | 1992

Extensible risc microprocessor architecture

Sanjiv Garg; Yasuaki Hagiwara; Tei-Li Lau; Derek J. Lentz; Yoshiyuki Miyayama; Le Trong Nguyen; Quang H. Trang; Johannes Wang

Archive | 1992

High performance RISC microprocessor architecture

Sanjiv Garg; Yasuaki Hagiwara; Tei-Li Lau; Derek J. Lentz; Yoshiyuki Miyayama; Le Trong Nguyen; Quang H. Trang; Johannes Wang

Archive | 1992

Risc microprocessor architecture with isolated architectural dependencies

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Quang H. Trang; Te-Li Lau

Archive | 2008

WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LISTHigh-performance, superscalar-based computer system with out-of-order instruction execution

Le-trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Te-Li Lau; Sze-Shun Wang; Quang H. Trang

Archive | 1992

RISC-PROZESSOR MIT DEHNBARER ARCHITEKTUR

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Tei-Li Lau; Quang H. Trang

Archive | 1992

Risc-prozessor mit dehnbarer architektur RISC processor with extensible architecture

Le Trong Nguyen; Derek J. Lentz; Yoshiyuki Miyayama; Sanjiv Garg; Yasuaki Hagiwara; Johannes Wang; Tei-Li Lau; Quang H. Trang

Archive | 1992

Architecture de microprocesseur RISC à hautes performances

Sanjiv Garg; Yasuaki Hagiwara; Tei-Li Lau; Derek J. Lentz; Yoshiyuki Miyayama; Le Trong Nguyen; Quang H. Trang; Johannes Wang

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Epson

Archive Network Publication Hotspot Collaboration

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot

Dive into the research topics where Quang H. Trang is active.

Publication

Featured researches published by Quang H. Trang.

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

RISC microprocessor architecture implementing fast trap and exception state

Extensible risc microprocessor architecture

High performance RISC microprocessor architecture

Risc microprocessor architecture with isolated architectural dependencies

WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LISTHigh-performance, superscalar-based computer system with out-of-order instruction execution

RISC-PROZESSOR MIT DEHNBARER ARCHITEKTUR

Risc-prozessor mit dehnbarer architektur RISC processor with extensible architecture

Architecture de microprocesseur RISC à hautes performances

Collaboration

Dive into the Quang H. Trang's collaboration.

Archive Network Publication Hotspot Collaboration

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot

Dive into the research topics where Quang H. Trang is active.

Publication

Featured researches published by Quang H. Trang.

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

RISC microprocessor architecture implementing fast trap and exception state

Extensible risc microprocessor architecture

High performance RISC microprocessor architecture

Risc microprocessor architecture with isolated architectural dependencies

***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***High-performance, superscalar-based computer system with out-of-order instruction execution

RISC-PROZESSOR MIT DEHNBARER ARCHITEKTUR

Risc-prozessor mit dehnbarer architektur RISC processor with extensible architecture

Architecture de microprocesseur RISC à hautes performances

Collaboration

Dive into the Quang H. Trang's collaboration.

WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LISTHigh-performance, superscalar-based computer system with out-of-order instruction execution