Quentin Morrissey

A large-area CMOS monolithic active pixel sensor for extreme ultraviolet spectroscopy and imaging

We describe our programme to develop science-grade CMOS active pixel sensors for future space science missions, and in particular an extreme ultra-violet spectrograph for solar physics studies on the ESA Solar Orbiter. Our goal is the development of a large format 4k x 4k pixel CMOS sensor with useful sensitivity in the extreme ultra-violet (EUV) for solar physics spectroscopy and imaging. Our route to EUV sensitivity relies primarily in adapting the back-thinning and rear-illumination techniques first developed for CCD sensors; however we are also exploring the alternative approach of using a front-etch to expose the CMOS photodiodes. We have successfully back-thinned several 525 x 525 prototype CMOS sensors and proved that the devices survived the process both structurally and functionally. We have also been successful in removing the oxide from the front side of a small array of pixels, using focused ion beam etching. Preliminary results from these pixels show they are sensitive in the Ultra Violet. We have also designed a working large format 4k x 3k prototype on a 0.25 micron CMOS imager process.

Solar intensity X-ray spectrometer (SIXS) ASIC for a large dynamic range onboard BepiColombo ESA mission to Mercury

The SIXS instrument is designed for detecting and measuring solar X-rays and solar energetic particles in a Mercury orbit onboard BepiColombo. The particle detector consists of a CsI(Tl) core detector and 5 GaAs surface detectors. The front-end electronics of the particle detector is implemented as an ASIC which requires a large dynamic range of 2,000e- to 1,500,000e- and an integral non-linearity (INL) < 3% for a temperature range of -30deg C to +55deg C. The SIXS ASIC test structure has been manufactured to determine performance of differential vs. single-ended designs for noise, power supply rejection and current consumption. The ASIC has 8 channels, each of which consists of a preamplifier, a CR-RC shaper, a peak hold, a comparator and a buffer, all designed using enclosed geometry transistors. There are 6 channels for GaAs detectors with 3 different preamplifier types consisting of a single-ended with pole zero compensation; single-ended without pole zero compensation and a differential configuration. There are 2 channels for Csl detectors with single- ended and differential preamplifier designs. This ASIC has been manufactured in a 0.35 mum CMOS process. The ASIC architecture and design flow are described including simulated and measured results.

CMOS Active Pixel Sensor Developments at the Rutherford Appleton Laboratory

This paper reports on an on-going research programme at the Rutherford Appleton Laboratory (RAL) to develop science-grade CMOS Active Pixel Sensors for space science missions in which compactness, low-mass, low-power, and greater radiation tolerance are advantageous.

A multi-channel CCD clock driver ASIC for space-based applications

A high voltage mixed signal ASIC is described that provides multiple fully programmable clock outputs capable of driving large format CCD capacitive electrodes. The COMET ASIC provides 6 independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and voltage swing required over a 409.6mA range, with edge speeds <15ns achievable for small loads. Setup and control of the ASIC is via a simple SPI interface with safety features to ensure correct sequencing of channel operation and prevent driver supply reverse biasing. The ASIC also features an under-voltage lock out circuit to safeguard the chip in the event of power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. The circuit is manufactured in a commercial 0.35um HV CMOS technology and uses established layout techniques to harden against both Total Ionising Dose (TID) and Single Event Latchup (SEL) radiation effects. The device has been manufactured and test results are shown.

A 128-channel event driven readout ASIC for the R3B tracker

R3B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams into and out of a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R3B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements.

A pair of custom ASICs for bias generation and clock buffering in space-based CCD camera systems

A pair of radiation hardened high-voltage mixed signal Application Specific Integrated Circuits (ASICs) are described that provide the biasing and clocking functions required to drive large format CCDs used for space-borne cameras and focal planes. The use of these ASICs allows the CCD drive electronics to be realised in a compact and energy efficient manner saving volume, mass, and power when compared with traditional space-qualified discrete implementations. The STAR ASIC provides 24 independent voltage outputs with a 32.736V range at 10 bit resolution and with <100μV noise. Each voltage output provides a drive current of up to +/-20mA and is stable for capacitive loads of up to 10μF. An on-board telemetry system featuring a 12-bit ADC and programmable gain buffer allows internal monitoring of the output voltages plus up to 32 single ended and 4 differential external voltages, such as from PRT bridge circuits for temperature monitoring. A simple SPI serial interface provides control and telemetry read back, while all required voltages and currents are generated from internal bandgap circuits. The COMET ASIC provides 6 fully independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and output slew rate required over a 409.6mA range, with edge speeds <15ns achievable for small loads. Setup and control of the ASIC is also via an SPI interface with integrated safety features to ensure correct sequencing of channel operation and to prevent reverse biasing of the driver programmable voltage supplies. The COMET ASIC also features an under-voltage lock out circuit to safeguard the chip in the event of unexpected power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. Both devices have been designed in a commercial 0.35μm 50V tolerant HV CMOS technology using Triple Module Redundancy (TMR) and established layout techniques to harden against Total Ionising Dose (TID), Single Event Upset (SEU), and Single Event Latch-up (SEL) radiation effects. The latch-up detection circuits often needed for space electronics are therefore not required for either ASIC. Details of the architectures and circuit implementations of both ASICs will be presented. Test results from manufactured devices will be shown under representative load conditions.

A readout ASIC for the R 3 B silicon tracker

A 128-channel event-driven ASIC is described which reads out the R3B (Reactions with Relativistic Radioactive Beams) silicon micro vertex tracker. Ionizing particles with energies in the range of 40keV-50MeV are detected, digitized and read out with 12 bit resolution, and time stamped with up to 5ns precision. The ASIC copes with signal charges and detector leakage currents of both polarities and allows charge sharing to be taken into account by reading out the charge from neighboring channels. The ASIC can recover quickly from signals up to 1Gev, can store up to 32 events and can be easily daisy-chained to reduce parallel connections. Outputs can be Manchester encoded to allow for capacitive coupling of the data, and a 128-bit OR of all the channel hits provides a fast trigger output.

Solar Intensity X-Ray Spectrometer (SIXS) ASIC onboard the ESA BepiColombo mission to Mercury

The new SIXS prototype ASIC has been designed for detecting and measuring solar X-rays in a Mercury orbit onboard BepiColombo. The SIXS detector consists of a CsI(Tl) core detector and 5 Silicon surface detectors. This new ASIC has undergone major modifications and has a new differential charge preamplifier without any pole zero cancellation and has a large dynamic range of 2,000e- to 1,500,000e-. The ASIC has 8 channels, each of which consists of a preamplifier, a CR-RC shaper, a peak detect hold, a comparator, a buffer, and a new 8 bit resistor string DAC which sets the programmable threshold for the comparator There are 6 channels for Si detectors with a shaping time of 1 ¿s and 2 channels for CsI detector with a shaping time of 3 ¿s, one of which has twice the gain to accommodate for low output efficiency of the detector. The channels are multiplexed to a single 10/11 bit SAR ADC which runs at a 10 MHz clock and additional on chip programmable phase shifted clocks and programmable Upper and Lower threshold voltages. This ASIC has been manufactured in a 0.35 ¿m CMOS process using enclosed geometry transistors. All digital logic in the ASIC including control and ADC logic use voting logic flipflops for SEU prevention.

A Programmable Analogue Front-End ASIC for Gas Micro-Strip Detectors having a wide range of Input Capacitance

The FREDA ASIC is a new mixed signal ASIC for the HOT series gas micro strip detectors. These detectors have 512 channels each having different capacitance ranging from 2pF-80pF. This new ASIC is an upgrade to the previous programmable version of FREDA with new signal processing capabilities. It is a 16 channel ASIC each of which consists of a Peak Detect and De-randomiser, 8bit counter, 12 bit hybrid SAR ADC with multiplexed LVDS outputs in addition to a preamplifier, a programmable CR-RC shaper and a programmable gain amplifier. The peak detect de-randomiser is a 3 bit analogue peak hold pipeline to store randomly arriving pulses at an average data rate of 1MHz. It also allows baseline measurements of the shaper output during low periods to activity to enable correlated double sampling. A 100MHz, 8 bit counter is used to generate a timestamp which is controlled by the peak detect signal. The 12 bit hybrid SAR ADC generates its 4MSBs from a resistor string and the rest 8 bits from a capacitor bank, it uses a 20MHz clock and takes 800ns for a single data conversion. This ASIC has been manufactured using a 0.35m CMOS process. The ASIC architecture is described including simulated and measured results.