R.A.R. Young

High Temperature Digital and Analogue Integrated Circuits in Silicon Carbide

Silicon Carbide devices are capable of operating as a semiconductor at high temperatures and this capability is being exploited today in discrete power components, bringing system advantages such as reduced cooling requirements [1]. Therefore there is an emerging need for control ICs mounted on the same modules and being capable of operating at the same temperatures. In addition, several application areas are pushing electronics to higher temperatures, particularly sensors and interface devices required for aero engines and in deep hydrocarbon and geothermal drilling. This paper discusses a developing CMOS manufacturing process using a 4H SiC substrate, which has been used to fabricate a range of simple logic and analogue circuits and is intended for power control and mixed signal sensor interface applications [2]. Test circuits have been found to operate at up to 400°C. The introduction of a floating capacitor structure to the process allows the use of switched capacitor techniques in mixed signal circuits operating over an extended temperature range.

Electrical stability impact of gate oxide in channel implanted SiC NMOS and PMOS transistors

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

Realization of SiC-current limiting devices for serial protection of aircraft electronics

The wide-scale application of composite materials, such as carbon, aramid and glass fiber reinforced plastic, in aircraft fuselage to improve the fuel efficiency, have made the modern designs more susceptible to lightning strikes[1]. Widely used surge protection techniques, such as high power silicon zeners “tranzorbs”, metal oxide varistors and gas discharge tubes-based suppressors, are mostly incompatible with modern designs since the surge level could significantly rise, which generally results in larger components [2]. Under typical conditions, the peak voltage could be as high as ± 3.8 kV, while impedances are low. Realization of high performance current limiters, which could survive the combination of high-voltage and high temperature, is essential to overcome the issue of low impedance met in composite airframe environments [3].

High Temperature CMOS Circuits on Silicon Carbide

This paper presents the characteristics and performance of a range of Silicon Carbide (SiC) CMOS integrated circuits fabricated using a process designed to operate at temperatures of 300°C and above. The properties of Silicon carbide enable both n-channel and p-channel MOSFETS to operate at temperatures above 400°C [1] and we are developing a CMOS process to exploit this capability [4]. The operation of these transistors and other integrated circuit elements such as resistors and contacts is presented across a temperature range of room temperature to +400°C. We have designed and fabricated a wide range of test and demonstrator circuits. A set of six simple logic parts, such as a quad NAND and NOR gates, have been stressed at 300°C for extended times and performance results such as propagation delay drive levels, threshold levels and current consumption versus stress time are presented. Other circuit implementations, with increased logic complexity, such as a pulse width modulator, a configurable timer and others have also been designed, fabricated and tested. The low leakage characteristics of SiC has allowed the implementation of a very low leakage analogue multiplexer showing less than 0.5uA channel leakage at 400°C. Another circuit implemented in SiC CMOS demonstrates the ability to drive SiC power switching devices. The ability of CMOS to provide an active pull up and active pull down current can provide the charging and discharging current required to drive a power MOSFET switch in less than 100ns. Being implemented in CMOS, the gate drive buffer benefits from having no direct current path from the power rails, except during switching events. This lowers the driver power dissipation. By including multiple current paths through independently switched transistors, the gate drive buffer circuit can provide a high switching current and then a lower sustaining current as required to minimize power dissipation when driving a bipolar switch.

Charge Pumping Analysis of Monolithically Fabricated 4H-SiC CMOS Structures

The development of silicon carbide complimentary metal-oxide-semiconductor (CMOS) is a key-enabling step in the realisation of low power circuitry for high-temperature applications. This paper describes investigations using the charge pumping technique into the properties of the gate dielectric interface as part of the development of the technology to realise monolithic fabrication of both n and p channel devices. A comparison of the charge pumping technique and the Hill-Coleman and Terman methods is also carried out to explore the feasibility of the technique.

First Demonstration of High Temperature SiC CMOS Gate Driver in Bridge Leg for Hybrid Power Module Application

A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond.

SiC current limiting devices for surge protection

Current limiting devices (CLD), which employ back-to-back connected high voltage normally-ON SiC-based vertical junction filed effect transistors (VJFETs), are realized to protect the sensitive aircraft electronics from the adverse effects of a lightning strike to the airframe. The functionality of the packaged CLDs with high and low current levels is demonstrated in low voltage static and transient tests. Electro-thermal simulations are performed to optimize the thermal performance of CLDs for high-energy test environments.

Influence of Phosphorous Auto-Doping on the Characteristics of SiO2/SiC Gate Dielectrics

We present the influence of phosphorous auto-doping on the characteristics of the oxide interface in 4H-SiC following high temperature gate oxide annealing. IV characteristics show no evidence of direct tunnelling breakdown; however Fowler Nordheim (F-N) conduction is observed in high electric field with the oxides able to sustain >10MV/cm. Capacitance Voltage data show DIT <1x1012 eV-1cm-2 close to the conduction band edge after POA, with undoped samples demonstrating DIT below 5x1011 eV-1cm-2. Photo CV data indicates smaller flat band voltage shifts of 0.6V at midpoint for the undoped samples, in comparison to 0.9V for the phosphorous doped devices. Temperature and bias stress tests at 200°C showed marginal hysteresis (0.3V) in both wafers. Reliability of time-dependent constant current and constant voltage characteristics revealed higher TDDB lifetimes in the undoped wafer. We conclude that the unintentional incorporation of phosphorous into the gate stack as a result of high temperature POA of the doped field oxide leads to a variation in flat band shift, higher DIT, and lower dielectric reliability.

Low Frequency Noise Analysis of Monolithically Fabricated 4H-SiC CMOS Field Effect Transistors

Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.

Comparison of Oxide Quality for Monolithically Fabricated SiC CMOS Structures

The recent development of silicon carbide complimentary metal-oxide-semiconductor (CMOS) is a key enabling step in the realisation of low power circuitry for high temperature applications, such as aerospace and well logging. This paper describes investigations into the properties of the gate dielectric as part of the development of the technology to realize monolithic fabrication of both n and p channel devices. A comparison of the oxide quality of the silicon carbide CMOS transistors is performed to examine the feasibility of this technology for high temperature circuitry.