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Dive into the research topics where R. B. Ahmad is active.

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Featured researches published by R. B. Ahmad.


ieee business engineering and industrial applications colloquium | 2013

Effect of relay location on two-way DF and AF relay for multi-user system in LTE-A cellular networks

Jaafar A. Aldhaibani; A. Yahya; R. B. Ahmad; Normaliza Omar; Zaid G. Ali

In order to meet the increasing demand and stringent design requirements for coverage expansion, throughput and capacity enhancement relay Node (RNs) has been considered as a promising solution to LTE-A Point-to-Multi-Point (PMP) networks. In this paper two scenarios are proposed, at the first scenario this work introduced the performance analysis of two-way Multiuser system of half duplex to AF (Amplify and Forward) and DF (Decoded and Forward) Relay. At the second scenario the position of a relay problem for the maximum capacity enhancement of a two-way Relay Node (RN) to achieve an efficient and scalable Long Term Evolution-Advanced (L TE-A) wireless network design is investigated., the optimum relay location that provides the greatest achievable rate with two-way performance is derived. It has been observed from the results that the optimum location of AF relay is 0.72 of the cell coverage radius, whereas the DF relay achieved a maximum bit rate when the relay location is at 0.52 from the cell coverage radius. The proposed method will help LTE-A designer to solve relay placement problem.


international conference on electronic design | 2008

A survey on on-demand multipath routing protocol in MANETs

N.Z. Ali; R. B. Ahmad; S.A. Aljunid

A mobile ad hoc networks (MANETs) consist of a collection of wireless mobile nodes which dynamically exchange data among themselves without a reliance on a fixed base station or a wired backbone network. Because of these characteristics, path connecting source nodes with destination may be very unstable and go down at any time, making communication over ad hoc networks difficult. In most cases, the ability of creating multiple routes from source to destination is used to provide a backup route. When a primary route fails to deliver the packets in some wa, the backup is used. This provides a better fault tolerance in the sense of faster and efficient recovery from route failures. This paper will address the previous study on multipath routing protocols in MANETs, benefits and applications.


international conference on electronic design | 2008

Link availability estimation for routing metrics in MANETs : An overview

N.Z. Ali; R. B. Ahmad; S.A. Aljunid

A mobile ad hoc network (MANET) is a collection of wireless mobile terminals that are able to dynamically form a temporary network without any aid from fixed infrastructure or centralized administration. MANETs are strongly impacted by the mobility of the ad hoc nodes. Path broken, which is caused by node mobility , leads to the rerouting operations and the degradation of network performance. One critical issue for routing in MANETs is how to select reliable path that can last as long as possible. This paper will address the previous study on how to measure link availability or reliability in order to find more reliable paths. To solve this problem, a criterion that can judge the link reliability is needed. The metric for routing selection in terms of path availability which is based on link availability can be used to select reliable path.


international conference on computer and communication engineering | 2008

FPGA based control IC for multilevel inverter

Mutmid Ahmad; Z. Husin; R. B. Ahmad; H.A. Rahim; M.S. Abu Hassan; M.N. Md Isa

Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower THD, lower EMI generation, better output waveform and higher efficiency for a given quality of output waveform. This paper presents the development of Altera FPGA as a control circuit for multilevel PWM single phase inverter. The FPGA chip produce 16 control signal for 9 level output voltage. Cyclone FPGA chip is a programmable logic device develop by Altera and can be considered as an efficient hardware for rapid prototyping. FPGA chip is chosen for the hardware implementation of control circuit is due to its high computation speed that can produce accurate control signal. Internal architecture of control circuit embeds in FPGA are described in detail. VHDL language is used to model the switching strategies and Quartus II software is used as a simulation and compiler tool. The results of compilation consist of 1250 logic elements with 9 level output voltage.


ieee symposium on industrial electronics and applications | 2011

Hybrid OCDMA/WDM system using complementary detection technique for FTTH access networks

N. Ahmed; S. A. Aljunid; A. Fadil; R. B. Ahmad; M. A. Rashid

A hybrid optical code division multiple access (OCDMA) over wavelength division multiplexing (WDM) system is proposed for supporting large numbers of subscriber for fiber-to-the-home (FTTH) network. The system combines two different techniques, namely OCDMA and WDM in order to support many subscribers simultaneously. In this study, the modified double weight (MDW) code is used as signature address in designing the system because this code can accommodate more number of simultaneous active users under standard acceptable bit-error-rate (e.g. ≤ 10−9). The complementary subtraction detection technique is used to detect the signal. The MDW code is better than other codes for improving the system performance by reducing the multiuser interference in a significant amount. We ascertained by simulation experiments that the proposed system provides high impact performance and enhance the network capacity.


information sciences, signal processing and their applications | 2010

Vehicle speed detection using frame differencing for smart surveillance system

H. A. Rahim; Usman Ullah Sheikh; R. B. Ahmad; A. S. M. Zain; Wan N. F. Wan Ariffin

This paper presents vehicle speed detection algorithm and its application for smart surveillance system using PC workstation at the selected road lane. Typical temporal resolution of 30 ms to 40ms of conventional camera has been utilized. The resolution is limited to the frame-rate of camera where the maximum velocity that can be computed depends on two factors: the timing resolution and the displacement resolution in pixels on image. The speed estimation of car and motorcycle are obtained in real-time using frame differencing technique for moving object detection. Experimental results are presented to demonstrate the efficiency of the proposed algorithm where it has been tested on a real video sequence and the results are analyzed.


asia international conference on modelling and simulation | 2008

The Performance Study of Two Genetic Algorithm Approaches for VLSI Macro-Cell Layout Area Optimization

Herlina Abdul Rahim; Azrul Azwan Abdul Rahman; R. B. Ahmad; Wan N. F. Wan Ariffin; M.I. Ahmad

Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed chip. The VLSI cell area optimization continues to become increasingly important to the performance of VLSI design due to the accelerating of the design complexities in VLSI. Thus, this paper addresses the performance comparisons of two different types of genetic algorithm (GA) techniques for VLSI macro-cell layout area optimization by utilizing the adopted method of cell placement that is binary tree method. Two GA approaches which are simple genetic algorithm (SGA) and steady-state genetic algorithm (SSGA) have been implemented and their performances in converging to their global minimums are examined and discussed. The performances of these techniques are tested on Microelectronics Center of North Carolina (MCNC) benchmark circuits data set. The experimental results demonstrate that both algorithms achieve acceptable area requirement compared to the slicing floorplan approach (Lin et al., 2002). However, SSGA outperforms SGA where it achieves faster convergence rate and obtains more near optimum area.


ieee international conference on photonics | 2012

Modeling and simulation of variable weight zero cross correlation code in optical access network

M.N. Junita; S. A. Aljunid; M. S. Anuar; A. R. Arief; Rosemizi Abd Rahim; R. B. Ahmad; M.N. Saad

In this paper, we demonstrate a novel architecture of variable weight Zero Cross Correlation code in the family of Spectral Amplitude Coding(SAC) Optical Code Division Multiple Access (OCDMA) to be utilized in the triple play services of OCDMA applications based on the end users demand and requirements. This is achieved by adapting multiple weights of Zero Cross Correlation (ZCC) code onto one system to accommodate different Quality of Service (QoS) requirements. The results are characterized by bit error rate (BER) and eye pattern simulated using OptiSystem software. Results proved a successful transmission of this scheme over 20km distance thus offering flexibility of independent QoS. It is also revealed that the performance is always better for users with larger number of code weight compared to those assigned with smaller code weight.


international conference on computer science and education | 2011

Performance comparison of Single Board Computer: A case study of kernel on ARM architecture

Naufal Alee; Mostafijur Rahman; R. B. Ahmad

Due to increase computer hardware technologies, software developers are more focusing on to developing embedded operating system. GNU/Linux becomes a common operating system widely use in embedded technologies. In this paper, we report performance results on a TS-7800 Single Board Computer with different version of kernel that has been released by hardware provider. We compare the performance between operating system with the latest kernel given by hardware provider, Linux kernel (2.6.34) and the previous kernel (2.6.21) Our results indicate that the new kernel has better performance in kernel benchmark, more bandwidth and less latency. In other experiments we found that the results are almost the same and in some cases the kernel (2.6.21) has better performance than the kernel (2.6.34).


international conference on computer and communication engineering | 2010

An adapted point based tracking for vehicle speed estimation in linear spacing

H. A. Rahim; R. B. Ahmad; A. S. M. Zain; Usman Ullah Sheikh

Vehicle velocity estimation is an important aspect of intelligent transportation systems. Normally velocity is estimated using dedicated laser speed traps and Doppler radars. Recently, the use of cameras is becoming more common for the purpose of traffic surveillance and smart surveillance system. It is thus the aim of this paper to propose a method for vehicle speed estimation using these existing video cameras. In this paper, we propose a vehicle speed estimation method from video analysis. The method proposed contains several steps; image preprocessing, centroid extraction and tracking. The proposed method transforms the 2D image points into a 3D virtual world to obtain actual vehicle position in 3D space. This is to account for perspective distortion commonly seen in images. Using these 3D points and measuring the time for displacement, the vehicle speed is obtained. Experimental results have shown that the proposed method gives accurate velocity estimation.

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S. A. Aljunid

Universiti Malaysia Perlis

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N. Ahmed

Universiti Malaysia Perlis

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Hilal A. Fadhil

Universiti Malaysia Perlis

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A. S. M. Zain

Universiti Malaysia Perlis

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H. A. Rahim

Universiti Malaysia Perlis

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I. Iszaidy

Universiti Malaysia Perlis

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Mostafijur Rahman

Universiti Malaysia Perlis

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Abid Yahya

Botswana International University of Science and Technology

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M. I. Jais

Universiti Malaysia Perlis

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