R.G. Deshmukh

Design of a tokenless architecture for parallel computations using associative dataflow processor

The currently existing models of computation, control-flow and data-flow, have their limitations and weaknesses in utilizing parallelism adequately. A new refined model of computation, called associative dataflow, has been previously proposed in the literature which attempts to circumvent the bottlenecks inherent in conventional dataflow using associative memories. In this new model of computation, a dataflow graph is conceptually assumed to be upside-down and the computation is divided into two phases, namely the search phase and the execution phase. During the search phase, each node at the top of the hierarchy, called the parent, attempts to find the nodes connected to it in the dataflow graph, called the children. During the execution phase, the operations are carried out as in conventional dataflow paradigm. The limitations and weaknesses associated with control-flow and data-flow are described, leading to the proposed concept of associative dataflow. Simulation results of existing dataflow systems are compared with the associative dataflow model to support the fact that the new model of computation provides faster execution time and better ALU utilization than the conventional models. The design of an associative dataflow system is described by providing as much detail as can possibly be incorporated to understand the concept with reference to existing computer systems. Finally, specifications of the designed system are outlined by listing important characteristics of the associative dataflow system.

Problems in robotic vision

The problems and choices that are faced when designing an automated vision system are examined. The tradeoffs between the different choices are considered. Particular attention is given to digitization and sampling, the preprocessing of digital images, histograms, threshold adoption/contrast stretching, edge and boundary detection, and search methods.<<ETX>>

Complex number representation in RCBNS form for arithmetic operations and conversion of the result into standard binary form

We introduce a novel method for complex number representation. The proposed, redundant complex binary number system (RCBNS) is developed by combining a redundant binary number and a complex number in base (-1+j). Donald (1960) and Walter Penny (1964, 1965) represented complex numbers using base -j and (-1+j) in the classified algorithmic models. A redundant complex binary number system consists of both real and imaginary-radix number systems that form a redundant integer digit set. This system is formed by using complex radix of (-1+j) and a digit set of /spl alpha/=3, where /spl alpha/ assumes a value of -3, -2, -1, 0, 1, 2, 3. The arithmetic operations of complex numbers with this system treat the real and imaginary parts as one unit. The carry-free addition has the advantage of redundancy in number representation in the arithmetic operations. Results of the arithmetic operations are in the RCBNS form. The two methods for conversion from the RCBNS form to the standard binary number form have been presented. The RCBNS reduces the number of steps required to perform complex number arithmetic operations, thus enhancing the speed.

A novel fault-detection technique for the parallel multipliers and dividers

A new fault-detection technique, /spl omega/-scan, for a specific interconnection of the parallel Braun-multiplier and the parallel divider is presented. The fault-detection model, Pair Faults (pf), and the concept of Multiple Fault Boundaries (MFBs) are generalized with new supporting lemmas. The new techniques application is used to detect all multiple stuck-at faults of the carry save adder (CSA) tree and the adder-subtractor (AS) tree with or without being iterative logic arrays (ILAs) and with or without summand-generator embodiment. Fault location is limited. There are 2(n+2) test patterns to be applied to an n/spl times/n CSA tree and its associated test gates and 2(n+4) patterns to an m/n AS tree only.

An algorithm to determine shortest length distinguishing, homing, and synchronizing sequences for sequential machines

The objective of this paper is to analyze the behavior of sequential machines by experimental means. Experiments are concerned with state-identification to identify the initial and final state of the machine. A computer program is developed which accepts, as input, a state table of Mealy type (any number of states) machine and builds the successor trees and finds the minimized distinguishing, homing, and synchronizing sequences. The program identifies the levels of the nodes and also lists all groups at each successor node of the tree. Additionally, flags are set when a terminal node is reached or a solution is obtained. The program, written in Pascal, is executed on the Vax 11/780 computer.

A novel approach to design a massively parallel application specific architecture for image recognition systems

The goal of the paper is to present a novel approach for designing massively parallel architectures for image recognition systems. Massive parallel hardware produces high speed image recognition. Hardware architectures work much faster and are more effective for application specific processing than a software-based image recognition system. The concept of designing optimal image recognition systems with high speed, low complexity, good portability, and low cost has been present for a long time. The authors have considered the basic design factors, simple and regular design, concurrency and communication, and balancing computation with I/O. The technique presented provides a new method of designing an image recognition system by concentrating on modularity and massive parallelism. This is accomplished through the design of a processing element layer, local communicator layer, and network of new image layer. The processing element (PE) layer performs the basic recognition functions on individual pixels through logical operations. Both the local communicator and network of new image layers institute a mesh network topology, which has proven to be the fastest and most efficient. The local communicator layer has the most important function, it communicates with the other two layers, combines results from the PE layer, and houses the main control unit. All layers work simultaneously, or in other words, in a parallel fashion. The flow diagram of a CAD designer algorithm, based on this new design technique, is presented.

A novel method for arithmetic operations using complex binary number system and the reconversion of the result to the decimal complex number system

Walter Penney defined a complex number system first by using a base of -4 and later by using (-1+j) [W. Penney, (1964), (1956)]. Other researchers have been working on the representation of complex binary numbers as one unit and perform arithmetic operations [(T.Jamil et al., (2000)]. We discuss a complex binary number system (CBNS) for high-speed arithmetic operations. An algorithm that performs the conversion of the decimal complex numbers to the binary complex number system that treats the complex number as one unit is represented [(T.Jamil (Dec2001)/Jan2002)]. A lookup table is generated to store their equivalent values in the CBNS form. We also present a new method to perform arithmetic operations (+, - , *, /) on operands in the CBNS form. A new algorithm is developed to add two complex numbers (CBNS form) using a modified carry look ahead principle. A block diagram for the adder that uses a new algorithm is presented. The results of the arithmetic operations in the CBNS form are reconverted back to the binary complex number using a new lookup table. This lookup table presents a new method for the reconversion of the CBNS numbers to the complex numbers.

An alternative method for designing parallel image recognition systems: a feasibility study

The most successful image recognition systems have been developed in software. This method has proved to be quite laborious and the execution time is intensive. An alternative method of designing image recognition systems is needed. The goal is to design a reliable, compact, high speed, low cost recognition system. One way to reach this goal is to design the image recognition system via a massively parallel hardware architecture. The present study researches the feasibility of developing a generalized procedure to design unique image recognition systems. These unique image recognition systems will incorporate special purpose processors that will work at a speed that is several orders of magnitude faster than software image processing systems. These systems have great application perspectives, especially in the robotics and industrial fields. One of the most important aspects of these systems-is the unique compact size as compared with other systems of comparable speed. Also, these systems are independent modules that will output, in most cases, a signal to a controller without the need to use a conventional computer or processor. The procedure to be developed provides a new way of designing an image processing system by concentrating on modularity and massive parallelism. Combining the modules will provide a special purpose processing system that achieves object detection and recognition at a high speed not even possible on a general purpose supercomputer. The other advantages include the low cost of implementation and the compact size of the whole system.

A novel technique for parallel computations using associative dataflow processor

The current microelectronics technology is expected to have the capability of 50-100 million transistors on a single chip by the year 2000. Such an on-chip hardware capacity motivates the development of a new generation of faster and more intelligent computers incorporating efficient techniques to handle computations. The prevalent concepts of control-flow and data-flow to build computers have their limitations and weaknesses in exploiting parallelism to the utmost limit. Therefore, a novel technique to handle parallel computations, called associative dataflow, is presented in this paper. In the proposed model of computation, the need for tokens is eliminated. The processing of a dataflow graph is accomplished in two phases. (1) The search phase: assuming the dataflow graph to be upside-down, each node at the top of the hierarchy, called the parent, looks for its descendants, called children, which are at the bottom of the hierarchy. This facilitates each node to know its data and destination(s) in the system. (2) The execution phase: the operations are performed, but now there is no delay in creating or matching tokens. This approach eliminates the major bottleneck in dataflow architectures, concerning the matching of tokens and the enhancement of their performance. Preliminary results have indicated a faster execution speed and higher ALU utilization for the proposed model compared to the conventional dataflow model. These results forecast a promising future for the associative dataflow model of computation.

Development of an identification method for fast routing

Introduces a novel method of routing that can be used where a vision system is required. This method provides high-accuracy object recognition, taking into account that it will be used in real-world surroundings, not clean-lab surroundings. The system has to tolerate different noisy environments and perform the assigned task using off-the-shelf equipment. Several programs were developed to accommodate the tasks that it would undertake. Object recognition is done by coding the object with a code that distinguishes it, without the need for matching the whole image.<<ETX>>