R. K. Chauhan

Analytical modelling of surface potential of modified source FD-SOI MOSFET

In this paper, a 2-D (two dimensional) analytical model for the surface potential variation forward to the channel in modified source fully depleted silicon on insulator (FD-SOI) n-MOSFET has been presented. In order to demonstrate the novel features offered by the modified source FD-SOI MOSFET n-MOSFET, the two dimensional surface potential model has also been investigated on various aspects such as effect of silicon film thickness variation and effects of different levels of source doping. And in continuation, to verify the short channel immunity of the device the surface potential model vs channel length for DIBL at different drain to source voltages has been discussed.

Performance Analysis of Fully Depleted SOI Tapered Body Reduced Source (FD-SOI TBRS) MOSFET for Low Power Digital Applications

The fully depleted silicon-on-insulator metal oxide semiconductor field effect transistor (FD- SOI MOSFET) have been considered a promising candidate to extend scaling of planar CMOS technology beyond 100 nm. This technology has been used to reduce leakage current, parasitic capacitances, and fabrication complexity as compared to planar CMOS technology at 50 nm gate length. This paper presents the performance analysis of proposed Tapered Body Reduced Source (FD-SOI TBRS) MOSFET. The proposed structure consumes less chip area and better electrical performance as compared to conventional FD-SOI MOSFET. The proposed structure exhibits higher Ion to Ioff ratio when compared with conventional FD-SOI MOSFET. The structures were designed and simulated using the Cogenda device simulator.

Performance Analysis of Fully Depleted Ultra Thin-Body (FD UTB) SOI MOSFET Based CMOS Inverter Circuit for Low Power Digital Applications

This paper demonstrates the integration of fully depleted ultra thin-body Silicon on Insulator MOSFET (FD UTB SOI n and p-MOSFET) into CMOS inverter circuit. The proposed MOS device shows the better Ion to Ioff ratio, lower subthreshold slope and low threshold voltage at 50 nm gate length. The proposed CMOS circuit shows the good inverter VTC curve, and minimum delay has been obtained at 50 nm gate length. The proposed structures were designed and simulated using Sentaurus device simulator.

Analysis of N + N − Epi-Source Asymmetric Double Gate FD-SOI MOSFET

The conventional scaling of device dimension uses high doping which leads to degraded mobility and large undesirable junction capacitances. This paper provides a new idea to overcome the short-channel effects (SCEs) in the MOSFETs whose gate length lies in the deep submicrometer range. Here asymmetric DG-FD-SOI MOSFET having N+N− epi-source is proposed whose performance is analyzed. The ION/IOFF ratio of the proposed device is nearly 1010 which is good enough for fast switching applications.

Area efficient layout design of CMOS circuit for high-density ICs

ABSTRACT Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Design of one-transistor SRAM cell for low power consumption

In this work one-transistor static random access memory cell (SRAM) to reduce power consumption using tunnel diode as basic latching circuit element is designed and simulated. The SRAM cell consists of a transistor (nMOSFET) having effective gate length of 18nm and a pair of Si-Ge Tunnel diode having current peak to valley current ratio (PVR) of value 1.67 each. The bistability of the back-to-back series connected tunnel diode pair is used to hold the states of the designed SRAM cell and the pass transistor is used to control the switching of the tunnel diode. The changing in the state of the designed SRAM is observed by the variation of drain current (ID) of the transistor. This SRAM cell highly reduces the power dissipation compared to conventional SRAM cell and other SRAM cell structures.

Fast and power efficient level shifter using FD SOI MOSFETS and widlar current mirror configuration

In this paper, two low voltage level shifters are designed which are fast and power efficient. The level shifters shift the level from subthreshold to above threshold voltage. The level shifters are designed at 65nm process technology. The first level shifter is designed by replacing the bulk MOSFET with the FD SOI MOSFET using HSPICE simulator. The other level shifter is designed by using SOI MOSFET instead of bulk MOSFET and a widlar current mirror. SOI MOSFET is used in order to reduce leakage currents that are induced due to scaling (reduction in leakage current also reduces the power dissipation in the level shifter). Here, the effects of using widlar current mirror over Wilson current mirror has been studied.

Performance analysis of N-type double gate junctionless transistor

In this paper, the TCAD simulation of charge plasma based double gate junction-less transistor with channel length of 18nm is analyzed. The structure shows better ION/OFF ratio(107) compared to the conventional junction less transistors (JLT). The use of charge plasma concept for inducing n+-n+-n+ regions and generating free charge carrier for conduction makes the process of fabrication easier for the designed structure. The designed device since works at work-function value of 4.74eV, it reduces the constraints of using high gate metal work-function for JLTs. The substrate region is lightly and uniformly doped, which results in decreased random dopant fluctuation and hence results in less variation in threshold voltage of the device. The sensitivity of device to various parameter variations is investigated.

Effects of rare earth materials on thin film devices

In this paper, the effects of rare earth materials on thin film devices has been discussed. In order to demonstrate the various effects caused by the rare earth materials, a simple Fully Depleted Silicon on Insulator (FD-SOI) MOSFET of gate length 28nm has been considered. The performance of the device is studied for different type of the rare earth (La2O3 and LaLuO3) materials, used as gate dielectric at different oxide thickness. Further the performance of the device is modelled for study of drain current. It is found that FD-SOI MOSFETs are showing better electrical behavior with rare earth materials and there is flexibility of oxide thickness reduction as compared to conventional materials available in the literature. The device is showing an improvement in its result of drive current (Ion) and off state leakage current (Ioff).

Impact of Ge substrate on drain current of Trigate N-FinFET

In this paper, impact of lightly doped Ge substrate on drain current of Trigate N-FinFET has been investigated. The result obtained was compared with heavily doped Si substrate N-FinFET. The highest peak saturated drain current was found to increased by 25% in input characteristics and 8% in output characteristics. The fin height kept constant, hence without affecting the area consumed. The simulation has been done using VISUAL TCAD.