R. L. Chu
National Tsing Hua University
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Featured researches published by R. L. Chu.
Applied Physics Letters | 2009
L. K. Chu; T. D. Lin; M. L. Huang; R. L. Chu; Che-Hao Chang; J. Kwo; M. Hong
Ga2O3(Gd2O3) (GGO) directly deposited on Ge substrate in ultrahigh vacuum, without a passivation layer such as GeOxNy or Si, has demonstrated excellent electrical performances and thermodynamic stability. Energy-band parameters of GGO/Ge have been determined by in situ x-ray photoelectron spectroscopy in conjunction with reflection electron energy loss spectroscopy and current transport of Fowler–Nordheim tunneling. A conduction-band offset and a valence-band offset of ∼2.3 and ∼2.42 eV, respectively, have been obtained. Moreover, self-aligned Ge pMOSFETs of 1-μm-gate length using Al2O3/GGO as the gate dielectrics have shown a high drain current and a peak transconductance of 252 mA/mm, and 143 mS/mm, respectively.
Applied Physics Express | 2013
R. L. Chu; Wei-Jen Hsueh; T. H. Chiang; Wei-Chin Lee; H. Y. Lin; Tsung-Da Lin; Gail J. Brown; Jen-Inn Chyi; Tsung-Shiew Huang; Tun-Wen Pi; J. Raynien Kwo; M. Hong
Y2O3 and Al2O3 were deposited onto GaSb(100) surfaces by molecular beam epitaxy and atomic layer deposition, respectively. Angle-resolved X-ray photoelectron spectroscopy and electrical measurements were used to probe the two oxide/semiconductor interfaces, which yielded very different behaviors. Highly surface-sensitive scans showed traces of SbOx and AsOx at the Y2O3 surface, which were removed during subsquent ALD Al2O3. The deposition of Y2O3 led to true inversion as indicated in capacitance–voltage (C–V) characteristics, small hysteresis and frequency dispersion, and low gate leakage. In contrast, for Al2O3/GaSb, the GaSb remained virtually intact, with Al2O3 bonding to the residual As, leading to poor C–V characteristics.
Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena | 2010
R. L. Chu; T. D. Lin; L. K. Chu; M. L. Huang; C. C. Chang; M. Hong; C. A. Lin; J. Kwo
High-κ dielectric Ga2O3(Gd2O3) (GGO) has been deposited on Ge (100) at room temperature using molecular beam epitaxy. In situ angular-resolved x-ray photoelectron spectroscopy on the GGO/Ge after gate dielectric deposition and 500°C postdeposition annealing has exhibited negligible Ge interdiffusion, thus revealing high thermal stability of the heterostructure. The CF4-plasma treatment on the passivated GGO/Ge has greatly improved the capacitance-voltage characteristics of the metal-oxide-semiconductor capacitors, besides the very low gate leakage current density of 3.2×10−9A∕cm2 at a flat-band voltage +1V. These excellent interfacial characteristics have been achieved without employing any intentional passivation layers.
Applied Physics Letters | 2014
R. L. Chu; Y. C. Liu; W. C. Lee; T. D. Lin; M. L. Huang; Tun-Wen Pi; J. Kwo; M. Hong
A high-quality high-κ/Ge interface has been achieved by combining molecule beam epitaxy grown Ge epitaxial layer and in-situ deposited high κ dielectric. The employment of Ge epitaxial layer has sucessfully buried and/or removed the residue of unfavorable carbon and native oxides on the chemically cleaned and ultra-high vacuum annealed Ge(100) wafer surface, as studied using angle-resolved x-ray photoelectron spectroscopy. Moreover, the scanning tunneling microscopy analyses showed the significant improvements in Ge surface roughness from 3.5 A to 1 A with the epi-layer growth. Thus, chemically cleaner, atomically more ordered, and morphologically smoother Ge surfaces were obtained for the subsquent deposition of high κ dielectrics, comparing with those substrates without Ge epi-layer. The capacitance-voltage (C-V) characteristics and low extracted interfacial trap density (Dit) reveal the improved high-κ/Ge interface using the Ge epi-layer approach.
Applied Physics Express | 2011
C. A. Lin; Hanchung Lin; T. H. Chiang; R. L. Chu; L. K. Chu; Tsung-Da Lin; Y.H. Chang; Wei-E Wang; J. Raynien Kwo; M. Hong
The interfacial density of states (Dit) distribution of high-κ dielectric Ga2O3(Gd2O3) [GGO] directly deposited on n-type Ge(100) without invoking any interfacial passivation layer (IPL) was established using conductance measurements and charge pumping (CP) technique. The conductance measurements yielded Dit values in the range of (1–4)×1011 cm-2 eV-1 from the mid-gap energy to the conduction band edge within the Ge band gap, which are consistent with the mean Dit value of ~2×1011 cm-2 eV-1 near the mid-gap obtained independently by the CP method. The flat Dit distribution at the conduction band edge compares favorably with those attained using IPLs such as SiO2/Si-cap and GeO2.
device research conference | 2010
L. K. Chu; R. L. Chu; C. A. Lin; T. D. Lin; T. H. Chiang; J. Kwo; M. Hong
When channel materials other than Si are being considered to enhance the carrier mobility, Ge has always been one viable candidate since it possesses higher carrier mobility than those of Si. However, it is difficult to achieve a high-quality oxide/Ge interface comparable to SiO<inf>2</inf>/Si due to unfavorable surface properties and water-soluble native oxides of Ge. Over the past 4–5 years, two major techniques have been shown to effectively passivate the Ge surface by utilizing Si(SiO<inf>2</inf>) [1] and thermally grown stoichiometric GeO<inf>2</inf> [2,3] as the passivation layers, thus giving low D<inf>it</inf>s of ∼10<sup>11</sup> cm<sup>−2</sup>eV<sup>−1</sup>. However, the use of the interfacial passivation layers (IPL) encountered a major hindrance primarily due to their relatively lower к values which have an adverse effect on the critical requirement of great reduction of equivalent oxide thickness (EOT) for future CMOS applications. An effective approach to achieve the ultimate EOT down-scaling is to directly deposit high-к dielectrics on Ge without IPLs, while maintaining a high к value and decent oxide/Ge interface quality.
symposium on vlsi technology | 2010
W. C. Lee; P. Chang; Y. J. Lee; M. L. Huang; T. D. Lin; L. K. Chu; Y. C. Chang; H. C. Chiu; Y.H. Chang; C. A. Lin; W. H. Chang; R. L. Chu; T. H. Chiang; Y. D. Wu; J. Kwo; M. Hong
We have achieved high device performance in self-aligned inversion-channel InGaAs MOSFETs, as well as a CET of < 1 nm, a D<inf>it</inf> ≤ 10<sup>11</sup> eV<sup>−1</sup>cm<sup>−2</sup>, and high-temperature thermal stability withstanding >850°C RTA in GGO and a CET of < 1 nm in ALD-HfO<inf>2</inf> on InGaAs. Remarkable device performances in self-aligned, inversion-channel Ge MOSFET using GGO without any interfacial passivation layers (IPLs), and inversion-channel and accumulation type GaN MOSFETs with high ks as gate dielectrics have also been attained. Interfacial characteristics including energy band parameters were studied using x-ray photoelectron spectroscopy (XPS).
ieee international conference on solid-state and integrated circuit technology | 2010
W. C. Lee; T. D. Lin; L. K. Chu; P. Chang; Y. C. Chang; R. L. Chu; H. C. Chiu; Cheng-Ming Lin; W. H. Chang; T. H. Chiang; Y. J. Lee; M. Hong; J. Kwo
Ultra-high-vacuum (UHV) deposited Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) [GGO] has been employed for passivating InGaAs and Ge, without using any interfacial paissivation layers (IPLs). The GGO/InGaAs and /Ge metal-oxide-semiconductor capacitors (MOSCAPs) have exhibited low capacitance-equivalent-thickness (CET) of less than 1nm in GGO, low interfacial densities of states (D<inf>it</inf>s) ∼ 10<sup>11</sup>eV<sup>−1</sup>cm<sup>−2</sup>, and thermal stability at high temperatures. The high-quality GGO and interfaces of GGO/InGaAs, and /Ge enable the fabrications of inversion-channel InGaAs and Ge MOS field-effect-transistors (MOSFETs) using a self-aligned process, leading to high drain currents, transconductances (G<inf>m</inf>), and carrier mobilities.
international symposium on vlsi technology, systems, and applications | 2009
L. K. Chu; T. D. Lin; C. H. Lee; L. T. Tung; W. C. Lee; R. L. Chu; Che-Hao Chang; M. Hong; J. Kwo
Ultra-high vacuum (UHV)-deposited high Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) was proved to passivate Ge effectively, as evidenced by comprehensive investigations including structural, chemical, and electrical analyses. The Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>)/Ge interface is revealed to be abrupt even being subjected to a 500°C anneal, a high κ value of 14.5, a low leakage current density of ∼10<inf>−9</inf>A/cm<sup>2</sup> with a Fowler-Nordheim tunneling behavior, and well-behaved C-V characteristics are achieved. Furthermore, Ge self-aligned pMOSFETs with Al<inf>2</inf>O<inf>3</inf>/ Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) as the gate dielectrics have demonstrated a high drain current and a peak transconductance up to 252mA/mm and 143mS/mm, respectively, of 1µm-gate length.
european solid state device research conference | 2009
L. K. Chu; R. L. Chu; M. L. Huang; L. T. Tung; T. D. Lin; Che-Hao Chang; J. Kwo; M. Hong
Excellent electrical performances have been demonstrated for the MOSCAPs and MOSFETs using Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) gate dielectrics deposited at room temperature on Ge(100) without employing any interfacial layers. In this work, we report a very low interfacial density of state (D<inf>it</inf>) of ∼2×10<sup>11</sup>cm<sup>−2</sup>eV<sup>−1</sup>, a low leakage current density (J<inf>g</inf>) of ∼10<sup>−9</sup>A/cm<sup>2</sup>, well-behaved capacitance-voltage (C-V) characteristics including an excellent quasi-static C-V curve along with a high efficiency of 80% for the Fermi-level movement near the mid-gap. In addition, a high saturation drain current and a high transconductance of 496µA/µm and 178µS/µm, respectively, for the 1µm-gate-length device have been obtained as well.