R. Piandani

The FPGA based trigger and data acquisition system for the CERN NA62 experiment

The main goal of the NA62 experiment at CERN is to measure the branching ratio of the ultra-rare K+??+? decay, collecting about 100 events to test the Standard Model of Particle Physics. Readout uniformity of sub-detectors, scalability, efficient online selection and lossless high rate readout are key issues. The TDCB and TEL62 boards are the common blocks of the NA62 TDAQ system. TDCBs measure hit times from sub-detectors, TEL62s process and store them in a buffer, extracting only those requested by the trigger system following the matching of trigger primitives produced inside TEL62s themselves. During the NA62 Technical Run at the end of 2012 the TALK board has been used as prototype version of the L0 Trigger Processor.

A high-resolution TDC-based board for a fully digital Trigger and Data AcQuisition system in the NA62 experiment at CERN

A time-to-digital converter-based system, to be used for most subdetectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital trigger and data acquisition system in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four high-performance time-to-digital converters (HPTDCs), measure hit times from subdetectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors, and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB developed by the Pisa NA62 group are extensively discussed and performance data are presented in order to show its compliance with the experiment requirements.

NaNet-10: A 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector

A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power. To ensure the real-time operation of the system, a dedicated data transport mechanism has been implemented: an FPGA-based Network Interface Card (NaNet-10) receives data from detectors and forwards them with low, predictable latency to the memory of the GPU performing the trigger algorithms. Results of the ring-shaped hit patterns reconstruction will be reported and discussed.

NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

Development of Network Interface Cards for TRIDAQ systems with the NaNet framework

NaNet is a framework for the development of FPGA-based PCI Express (PCIe) Network Interface Cards (NICs) with real-time data transport architecture that can be effectively employed in TRIDAQ systems. Key features of the architecture are the flexibility in the configuration of the number and kind of the I/O channels, the hardware offloading of the network protocol stack, the stream processing capability, and the zero-copy CPU and GPU Remote Direct Memory Access (RDMA). Three NIC designs have been developed with the NaNet framework: NaNet-1 and NaNet-10 for the CERN NA62 low level trigger and NaNet3 for the KM3NeT-IT underwater neutrino telescope DAQ system. We will focus our description on the NaNet-10 design, as it is the most complete of the three in terms of capabilities and integrated IPs of the framework.

The TEL62: A real-time board for the NA62 Trigger and Data AcQuisition. Data flow and firmware design

The main goal of the NA62 experiment at CERN SPS is to measure the branching ratio of the ultra-rare K+→π+νν decay, collecting about 100 events in two years of data taking to test the Standard Model of Particle Physics. Readout uniformity of sub-detectors, scalability, efficient online selection and lossless high rate readout are key issues. The TEL62 boards are the common blocks of the NA62 Trigger and Data AcQuisition (TDAQ) system. TEL62s process and store hits coming from the subdetectors in a buffer according to their timestamp, extracting only those requested by the trigger system, which merges trigger primitives also produced by TEL62s. The complete dataflow and firmware organization are described.

Studies of the effects of oxygen and CO 2 contamination of the neon gas radiator on the performance of the NA62 RICH detector

The NA62 RICH detector is used for the separation of pions and muons in the momentum range 15-35 GeV/c and is expected to provide a muon suppression factor better than 10-2. A prototype of the final detector equipped with about 400 PMs (RICH-400 prototype) was built and tested in a dedicated run in 2009. The π-μ separation was tested, as well as the effect of the contamination of the neon radiator with different amounts of oxygen and CO2. The μ misidentification probability is about 0.7% and the time resolution better than 100 ps in the whole momentum range. We did not observe any absorption of the light due to the contamination of the radiator, however an effect on the ring radius is clearly observed due to the change of the refractive index of the medium. The conclusion of the studies is that the amount of CO2 in the final detector should be known at the 10-3 level of precision or the quality of the pion identification could be seriously compromised.

Real-time heterogeneous stream processing with NaNet in the NA62 experiment

The use of GPUs to implement general purpose computational tasks, known as GPGPU since fifteen years ago, has reached maturity. Applications take advantage of the parallel architectures of these devices in many different domains. Over the last few years several works have demonstrated the effectiveness of the integration of GPU-based systems in the high level trigger of various HEP experiments. On the other hand, the use of GPUs in the DAQ and low level trigger systems, characterized by stringent real-time constraints, poses several challenges. In order to achieve such a goal we devised NaNet, a FPGA-based PCI-Express Network Interface Card design capable of direct (zero-copy) data transferring with CPU and GPU (GPUDirect) while online processing incoming and outgoing data streams. The board provides as well support for multiple link technologies (1/10/40GbE and custom ones). The validity of our approach has been tested in the context of the NA62 CERN experiment, harvesting the computing power of last generation NVIDIA Pascal GPUs and of the FPGA hosted by NaNet to build in real-time refined physics-related primitives for the RICH detector (i.e. the Cerenkov rings parameters) that enable the building of more stringent conditions for data selection in the low level trigger.

The NA62 Calorimeter Level 0 Trigger Operation and Performances

The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay

GPU-based low-level trigger system for the standalone reconstruction of the ring-shaped hit patterns in the RICH Cherenkov detector of NA62 experiment

K^+ \rightarrow \pi^+ \nu \bar{\nu}