R.S. Williams

DEPOSITION OF THREE-DIMENSIONAL GE ISLANDS ON SI(001) BY CHEMICAL VAPOR DEPOSITION AT ATMOSPHERIC AND REDUCED PRESSURES

This report summarizes observations of Ge island formation during growth on Si(001) by chemical vapor deposition from germane in the pressure range from 10 Torr to atmospheric pressure in a conventional epitaxial reactor. A four-step growth process is observed: (1) uniform pseudomorphic overlayer (“wetting’’ layer) formation; (2) three-dimensional island growth with a constant aspect ratio; (3) continued island growth with a constant diameter and increasing height; (4) rapid growth of larger, faceted islands. Ostwald ripening of the islands during continued heat treatment after terminating the deposition is slow compared to island formation and growth during deposition for the experimental conditions used.

State Dynamics and Modeling of Tantalum Oxide Memristors

A key requirement for using memristors in circuits is a predictive model for device behavior that can be used in simulations and to guide designs. We analyze one of the most promising materials, tantalum oxide, for high density, low power, and high-speed memory. We perform an ensemble of measurements, including time dynamics across nine decades, to deduce the underlying state equations describing the switching in Pt/TaOx/Ta memristors. A predictive, compact model is found in good agreement with the measured data. The resulting model, compatible with SPICE, is then used to understand trends in terms of switching times and energy consumption, which in turn are important for choosing device operating points and handling interactions with other circuit elements.

Sub-10 nm nanoimprint lithography by wafer bowing.

We introduce the concept of wafer bowing to affect nanoimprinting. This approach allows a design that can fit the key imprinting mechanism into a compact module, which we have constructed and demonstrated with an overlay and resolution of <0.5 microm and <10 nm, respectively. In the short term, this wafer bowing approach makes nanoimprint lithography much more accessible to a broad range of researchers. More importantly, this approach eliminates machine movement other than wafer bowing and shortens the mechanical path; these will enable the achievement of excellent patterning and overlay at a much lower cost. In the long term, wafer bowing is extensible to step-and-repeat printing for volume manufacturing.

Hybrid CMOS/memristor circuits

This is a brief review of recent work on the prospective hybrid CMOS/memristor circuits. Such hybrids combine the flexibility, reliability and high functionality of the CMOS subsystem with very high density of nanoscale thin film resistance switching devices operating on different physical principles. Simulation and initial experimental results demonstrate that performance of CMOS/memristor circuits for several important applications is well beyond scaling limits of conventional VLSI paradigm.

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

Demultiplexers for Nanoelectronics Constructed From Nonlinear Tunneling Resistors

When using linear resistors to implement nanoelectronic resistor-logic demultiplexers, codes can be used to improve the voltage margins of these circuits. However, the resistors which have been fabricated in nanoscale crossbars are observed to be nonlinear in their current versus voltage (I-V) characteristics, showing an exponential dependence of current on voltage; we call these devices tunneling resistors. The introduction of nonlinearity can either improve or degrade the voltage margin of a demultiplexer circuit, depending on the particular code used. Therefore, the criterion for choosing codes must be redefined for demultiplexer circuits built from this type of nonlinear resistor. We show that for well-chosen codes, the nonlinearity of the resistors can be advantageous, producing a better voltage margin than can be achieved with linear resistors

On the integration of memristors with CMOS using nanoimprint lithography

Memristors were vertically integrated with CMOS circuits using nanoimprint lithography (NIL), making a transistor/memeristor hybrid circuit. Several planarization technologies were developed for the CMOS substrates to meet the surface planarity requirement for NIL. Accordingly, different integration schemes were developed and optimized. UV-curable NIL (UV-NIL) using a double layer spin-on resists was carried out to pattern the electrodes for memristors. This is the first demonstration of NIL on active CMOS substrates that are fabricated in a CMOS fab. Our work demonstrates that NIL is compatible with commercial IC fabrication process. It was also demonstrated that the memristors are integratable with traditional CMOS to make hybrid circuits without changing the current infrastructure in IC industry.

Defect-tolerant molecular electronics

The integrated circuit, manufactured by optical lithography, has driven the computer revolution for three decades. If we are to continue to build complex systems of ever-smaller components, we must find a new technology that will allow massively parallel construction of electronic circuits at the atomic scale. Our Hewlett-Packard and University of California research team is currently developing the molecular electronics building blocks and computer aided design algorithms for a defect-tolerant reconfigurable architecture which allows one to electrically download the designed complexity of a computer into a chemically assembled regular but imperfect nanostructure.

Band offsets in transition-metal oxide heterostructures

We measured valence band offsets in Ta2O5?WO3, Ta2O5?Nb2O5 and WO3?Nb2O5 heterostructure couples by in situ x-ray photoelectron spectroscopy, immediately following the bi-layer growth in ultra-high vacuum. Conduction band offsets were estimated using the measured valence band offsets in conjunction with the literature values for the respective band gaps. The offsets between Ta2O5 and WO3 and between Ta2O5 and Nb2O5 layers were strongly asymmetric, with 0.8?1.1?eV (0.1?0.2?eV) barriers for the conduction (valence) bands, depending on the particular couple and the stacking sequence. Such asymmetry can be very useful in switching devices.

Metal-catalyzed silicon nanowires: control and connection

Self-assembled Si nanowires can be grown using chemical vapor deposition accelerated by metal catalyst nanoparticles. The diameter of the nanowires depends on the size of the nanoparticles, which in turn can be controlled by varying the amount of catalyst deposited and the annealing conditions. The nanowires make good electrical connection to the substrate on which they are grown. They generally grow epitaxially along <111> directions and can grow laterally from one vertical (111)-oriented surface toward another and make good mechanical and electrical connection to the second surface. The nanowires can serve as sensors or as the channels of field-effect transistors.