R. Staley

The ATLAS Level-1 Calorimeter Trigger

The ATLAS Level-1 Calorimeter Trigger uses reduced-granularity information from all the ATLAS calorimeters to search for high transverse-energy electrons, photons, τ leptons and jets, as well as high missing and total transverse energy. The calorimeter trigger electronics has a fixed latency of about 1 μs, using programmable custom-built digital electronics. This paper describes the Calorimeter Trigger hardware, as installed in the ATLAS electronics cavern.

Use of an FPGA to identify electromagnetic clusters and isolated hadrons in the ATLAS level-1 calorimeter trigger

Abstract At the full LHC design luminosity of 10 34 cm −2 s −1 , there will be approximately 10 9 proton–proton interactions per second. The ATLAS level-1 trigger is required to have an acceptance factor of ∼10 −3 . The calorimeter trigger covers the region | η |⩽5.0, and φ =0 to 2 π . The distribution of transverse energy over the trigger phase space is analysed to identify candidates for electrons/photons, isolated hadrons, QCD jets and non-interacting particles. The Cluster Processor of the level-1 calorimeter trigger is designed to identify transverse energy clusters associated with the first two of these. The algorithms based on the trigger tower energies which have been designed to identify such clusters, are described here. The algorithms are evaluated using an FPGA. The reasons for the choice of the actual FPGA being used are given. The performance of the FPGA has been fully simulated, and the expected latency has been shown to be within the limits of the time allocated to the cluster trigger. These results, together with the results of measurements made with real data into a fully configured FPGA, are presented and discussed.

The ATLAS level-1 calorimeter trigger architecture

The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em//spl tau/ cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC timing, trigger and control system (TTC). A common data merger module (CMM) uses field-programmable gate arrays (FPGAs) with multiple configurations for summing electron/photon and /spl tau//hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquisition (DAQ) system, and region-of-interest (RoI) data to the level-2 triggers. Extensive use of FPGAs throughout the system makes the trigger flexible and upgradable, and several architectural choices have been made to reduce the number of intercrate links and make the hardware more robust.

Production and testing of limited streamer tubes for the end-cap muon subdetector of OPAL

Abstract The construction and testing of plastic streamer tubes for use as a large-area muon detector at OPAL are described. The use of extruded Noryl coated with a new carbon-loaded vinyl resistive paint is found to give tubes that behave in a uniform and reliable manner.

Pre-production validation of the ATLAS Level-1 calorimeter trigger system

The Level-1 calorimeter trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along with a description of the methodology used to perform the tests

Beam tests of a prototype level-1 calorimeter trigger for LHC experiments

Abstract Beam tests of a first-prototype electromagnetic calorimeter trigger processor for LHC experiments are described. The synchronous, pipelined, digital processor built with ASICs, was successfully operated at the full LHC bunch-crossing frequency of 40 MHz. Real data signals were obtained from a liquid argon electromagnetic calorimeter. The measured performance of the electron/photon trigger algorithm is compared with Monte Carlo simulations.

HIPPI developments for CERN experiments

Attention is given to the High-Performance Parallel Interface (HIPPI), a new ANSI standard, using a minimal protocol and providing 100-Mbyte/s transfers over distances up to 25 m. Equipment using this standard is offered by a growing number of computer manufacturers. A commercially available HIPPI chipset allows low-cost implementations. A brief technical introduction to the HIPPI is given, followed by examples of planned applications in high-energy physics experiments, including the developments involving CERN: a detector emulator, a RISC, (reduced instruction set computer) processor based VMEconnection, a long-distance fiber-optics connection, and a HIPPI testbox.<<ETX>>

First data with the ATLAS Level-1 Calorimeter Trigger

The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects, and energy sums. The final system consists of over 300 custom-built VME modules, of several different types. The installation at ATLAS of these modules, and the necessary infrastructure, was completed at the end of 2007. The system has since undergone intensive testing, both in standalone mode, and in conjunction with the whole of the ATLAS detector in combined running. The final steps of commissioning, and experience with running the full-scale system are presented. Results of integration tests performed with the upstream calorimeters, and downstream trigger and data-flow systems, are shown, along with an analysis of the performance of the calorimeter trigger in full ATLAS data-taking. This includes trigger operation during the cosmic muon runs from before LHC start-up, and a first look at LHC proton beam data.

ATLAS level-1 calorimeter trigger: subsystem tests of a Jet/Energy-sum Processor module

The ATLAS Level-1 Calorimeter Trigger consists of a Preprocessor, a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce trigger multiplicities and total and missing energy for the final trigger decision. The trigger will also provide region-of-interest (RoI) information for the Level-2 trigger and intermediate results of the data acquisition (DAQ) system for monitoring and diagnostics by using readout driver modules (ROD). The Jet/Energy-sum Processor identifies and localises jets, and sums total and missing transverse energy information from the trigger data. The Jet/Energy Module (JEM) is the main module of the Jet/Energy-sum Processor. The JEM prototype is designed to be functionally identical to the final production module for ATLAS, and have the full number of channels. Three JEM prototypes have been built and successfully tested. Various test vector patterns were used to test the energy summation and the jet algorithms. Data communication between adjacent Jet/Energy Modules and all other relevant modules of the Jet/Energy-sum Processor has been tested. Recent test results using the Jet/Energy Module prototypes are presented and discussed.

One Size Fits All : Multiple Uses of Common Modules in the ATLAS Level-1 Calorimeter Trigger

The architecture of the ATLAS Level-1 Calorimeter Trigger has been improved and simplified by using a common module to perform different functions that originally required three separate modules. The key is the use of FPGAs with multiple configurations, and the adoption by different subsystems of a common high-density custom crate backplane that takes care to make data paths equal widths and includes minimal VMEbus. One module design can now be configured to count electron/photon and tau/hadron clusters, or count jets, or form missing and total transverse-energy sums and compare them to thresholds. In addition, operations are carried out at both crate and system levels by the same module design.