R. Szczygiel

Design and performance of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker

The ABCD design is a single chip implementation of the binary readout architecture for silicon strip detectors in the ATLAS semiconductor tracker. The prototype chip has been manufactured successfully in the DMILL process. In the paper we present the design of the chip and the measurement results. The basic analogue performance of the ABCD design has been evaluated using a prototype SCT module equipped with the ABCD chips. The digital performance has been evaluated using a general purpose IC tester. The measurements confirmed that all blocks of the ABCD design are fully functional and the chips meet all basic requirements of the SCT. Wafer screening has been performed using a customised wafer tester.

Progress in development of the readout chip for the ATLAS semiconductor tracker

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has entered a pre-production prototyping phase. Following evaluation of the ABCD2T prototype chip, necessary correction in the design have been implemented and the ABCD3T version has been manufactured in the DMILL process. Design issues addressed in the ABCD3T chip and performance of this pre-production prototype are discussed.

Performance of a 128 channel analogue front-end chip for read-out of Si strip detector modules for LHC experiments

We present a 128-channel analogue front-end chip, SCT128A-HC, for readout of silicon strip detectors employed in the inner tracking detectors of the LHC experiment. The chip is produced in the radiation hard DMILL technology. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in details in the test bench and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A-HC chips has been built and tested successfully in the lab with /spl beta/ particles as well as in the test beam. The results concerning the signal-to-noise ratio, noise occupancy, efficiency and spatial resolution are presented. The radiation hardness issues are discussed.

SCT128B : A PROTOTYPE CHIP FOR BINARY READOUT OF SILICON STRIP DETECTORS

Abstract We present a 128-channel prototype chip for the binary readout of silicon strip detectors which has been designed and manufactured in the radiation hard DMILL technology. The goal of this development was to demonstrate the feasibility of building in the DMILL technology, a radiation hard chip suitable for the binary readout architecture for the ATLAS SCT. A single chip comprises the front-end circuitry, the binary pipeline and the back end readout circuitry. The architecture as well as the designs of the individual blocks are discussed in the paper. Measurements confirm that full functionality of all blocks of the chip have been achieved at a clock frequency of 40xa0MHz, meeting the design specification.

Radiation hardness of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker

The radiation hardness requirements of the ABCD chip are driven by the radiation levels expected in the ATLAS SCT after 10 years of LHC operation, which are 10 Mrad of total ionising dose and 2×10 n/cm of 1 MeV eq neutron fluence for the displacement damages. The ABCD chip, comprising both analogue and digital circuitry and realised in a BiCMOS technology, is sensitive to ionisation effects as well as to displacement damages. The recent prototype of the ABCD chip, which meets all SCT requirements, has been irradiated separately with X-ray, neutrons from a nuclear reactor, and with 24 GeV protons. In the paper we present and discuss the radiation effects observed in the ABCD chip.

Recent aging studies for the ATLAS transition radiation tracker

The transition radiation tracker (TRT) is one of the three subsystems of the inner detector of the ATLAS experiment. It is designed to operate for 10 yr at the LHC, with integrated charges of /spl sim/10 C/cm of wire and radiation doses of about 10 Mrad and 2/spl times/10/sup 14/ neutrons/cm/sup 2/. These doses translate into unprecedented ionization currents and integrated charges for a large-scale gaseous detector. This paper describes studies leading to the adoption of a new ionization gas regime for the ATLAS TRT. In this new regime, the primary gas mixture is 70%Xe-27%CO/sub 2/-3%O/sub 2/. It is planned to occasionally flush and operate the TRT detector with an Ar-based ternary mixture, containing a small percentage of CF/sub 4/, to remove, if needed, silicon pollution from the anode wires. This procedure has been validated in realistic conditions and would require a few days of dedicated operation. This paper covers both performance and aging studies with the new TRT gas mixture.

Progress in the development of the DTMROC time measurement chip for the ATLAS Transition Radiation Tracker (TRT)

A 16-channel digital time-measurement readout chip (DTMROC) has been fabricated in the TEMIC/DMILL BI-CMOS radiation-hard process for the Large Hadron Collider (LHC) Transition Radiation Tracker (ATLAS/TRT) at CERN. The chip receives discriminated straw-drift-tube signals from bipolar amplifier-shaper-discriminator chips (ASDBLR), measures the arrival time in 3.125 ns increments (/spl plusmn/1 ns), and stores the data in a pipeline for 3.3 /spl mu/s. A trigger signal (L1A) causes the data to be tagged with a time stamp and stored for readout. Up to 13 events may be stored in an on-chip buffer while data is being clocked out in a 40 MHz serial stream. The chip has been designed to function after exposure to 1/spl times/10/sup 14/ protons/cm/sup 2/ and 1 Mrad total dose. System beam-tests have demonstrated measurement of track positions with a resolution of 165 /spl mu/m and 85% efficiency at rates up to 18 MHz.

Performance of the electrical module prototypes for the ATLAS silicon tracker

Electrical modules for the ATLAS Silicon Tracker (SCT) have been fabricated and tested. The modules consist of 6 ABCD front-end chips connected to silicon strip detectors, with the electronics hybrid and detector geometry as specified for the barrel and forward parts of the tracker. Tests were done with the second batch of the ABCD chip (ABCD2), connected to 6cm or 12cm long strip detectors. The functionality of the modules is demonstrated. The performance of modules depends on the signal gain in ABCD2 chips and on the grounding scheme. The design of the chip has been improved according to these observations. Recent results obtained with the new release of the chip (ABCD2T/NT) mounted on modules with 12cm strip detectors show the expected noise level of less than 1500 el., intrinsic stability and channel matching performance within 5%.

Progress in Development of the Analogue Read-out Chip for Silicon Strip Detector Modules for LHC Experiments

We present a new version of the 128-channel analogue front-end chip SCTA128VG for readout of silicon strip detectors. Following the early prototype developed in DMILL technology we have elaborated a design with the main goal of improving its robustness and radiation hardness. The improvements implemented in the new design are based on experience gained in DMILL technology while developing the binary readout chip for the ATLAS Semiconductor Tracker. The architecture of the chip and critical design issues are discussed. The analogue performance of the chip before and after the gamma irradiation is presented. The performance of modules built of ATLAS baseline detectors read out by six SCTA chips is briefly demonstrated. The performance of a test system for wafer screening of the SCTA chips is presented including some preliminary results.

Implementation of the DTMROC-S ASIC for the ATLAS TRT detector in a 0.25 /spl mu/m CMOS technology

The DTMROC-S is a 16-channel front-end chip developed for the signal processing of the ATLAS straw tube detector, TRT. Due to a highly radioactive environment, the chip is fabricated in a commercial 0.25 /spl mu/m CMOS technology hardened by layout techniques and, in addition, a special methodology was used to improve the circuits robustness against Single Events Effects (SEE) caused by ionizing particles. Exhaustive internal test features were foreseen to simplify and ensure comprehensive design verification, high fault coverage and throughput. Compared to the previous version of the chip done in a 0.8 /spl mu/m radiation-hard CMOS and despite of all supplementary features, the Deep-Sub-Micron (DSM) technology results in a much smaller chip size that increases the production yield and lowers the power consumption.